On 7/31/25 15:36, Alexandre Ghiti wrote:
> Hi Aleksa,
>
> On 7/24/25 17:23, Aleksa Paunovic via B4 Relay wrote:
>> This patch series adds support for the xmipsexectl vendor extension.
>> A new hardware probe key has also been added to allow userspace to probe for MIPS vendor extensions.
>>
>> Additionally, since the standard Zihintpause PAUSE instruction encoding is not supported on some MIPS CPUs,
>> an errata was implemented for replacing this instruction with the xmipsexectl MIPS.PAUSE alternative encoding.
>>
>> Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
>> ---
>> Changes in v5:
>> - Add MIPS.IHB and MIPS.EHB instructions
>> - Rebase on alex-for-next
>> - Address other smaller comments pointed out by Alexandre
>> - Link to v4: https://lore.kernel.org/r/20250625-p8700-pause-v4-0-6c7dd7f85756@htecgroup.com
>>
>> This is a continuation of a previous series, which did not implement the full
>> xmipsexectl vendor extension. The title was updated accordingly.
>>
>> Changes in v4:
>> - Add support for the xmipsexectl vendor extension
>> - Remove the ifdef/else from errata_list.h
>> - Replace the ifdef/else with a hwprobe call in the userspace code.
>>
>> Link to v3:
>> https://lore.kernel.org/linux-riscv/20250129131703.733098-1-arikalo@gmail.com/
>>
>> ---
>> Aleksa Paunovic (6):
>> dt-bindings: riscv: Add xmipsexectl ISA extension description
>> riscv: Add xmipsexectl as a vendor extension
>> riscv: Add xmipsexectl instructions
>> riscv: hwprobe: Add MIPS vendor extension probing
>> riscv: hwprobe: Document MIPS xmipsexectl vendor extension
>> riscv: Add tools support for xmipsexectl
>>
>> Djordje Todorovic (1):
>> riscv: errata: Fix the PAUSE Opcode for MIPS P8700
>>
>> Documentation/arch/riscv/hwprobe.rst | 9 +++
>> .../devicetree/bindings/riscv/extensions.yaml | 6 ++
>> arch/riscv/Kconfig.errata | 23 ++++++++
>> arch/riscv/Kconfig.vendor | 13 +++++
>> arch/riscv/errata/Makefile | 1 +
>> arch/riscv/errata/mips/Makefile | 5 ++
>> arch/riscv/errata/mips/errata.c | 67 ++++++++++++++++++++++
>> arch/riscv/include/asm/alternative.h | 3 +
>> arch/riscv/include/asm/cmpxchg.h | 3 +-
>> arch/riscv/include/asm/errata_list.h | 13 ++++-
>> arch/riscv/include/asm/errata_list_vendors.h | 5 ++
>> arch/riscv/include/asm/hwprobe.h | 3 +-
>> arch/riscv/include/asm/vdso/processor.h | 3 +-
>> arch/riscv/include/asm/vendor_extensions/mips.h | 37 ++++++++++++
>> .../include/asm/vendor_extensions/mips_hwprobe.h | 22 +++++++
>> arch/riscv/include/asm/vendorid_list.h | 1 +
>> arch/riscv/include/uapi/asm/hwprobe.h | 1 +
>> arch/riscv/include/uapi/asm/vendor/mips.h | 3 +
>> arch/riscv/kernel/alternative.c | 5 ++
>> arch/riscv/kernel/sys_hwprobe.c | 4 ++
>> arch/riscv/kernel/vendor_extensions.c | 10 ++++
>> arch/riscv/kernel/vendor_extensions/Makefile | 2 +
>> arch/riscv/kernel/vendor_extensions/mips.c | 22 +++++++
>> arch/riscv/kernel/vendor_extensions/mips_hwprobe.c | 23 ++++++++
>> arch/riscv/mm/init.c | 1 +
>> tools/arch/riscv/include/asm/vdso/processor.h | 27 +++++----
>> 26 files changed, 298 insertions(+), 14 deletions(-)
>> ---
>> base-commit: b6a4bae2f16162876842127d7507dad84e404f8f
>> change-id: 20250424-p8700-pause-dcb649968e24
>>
>> Best regards,
>
>
> Thanks for the v5, I'll take that for 6.17.
Hi Alexandre,
Thank you once again for taking the time to review the series.
Best regards,
Aleksa
>
> Thanks,
>
> Alex
>