From nobody Mon Oct 6 04:56:04 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A67532E9EB9; Thu, 24 Jul 2025 15:23:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753370614; cv=none; b=LEzlFbYWuEmXRlFOa5sMiWNOHvVDTHoQ+TXUcdYl0hAnyQk96YzTQ+K4rbop/X4GpZNmbsmQT+WBPuKIXTPr2VqasTnYGSvOwS4k6SntgobuBDX6xT0dIBlUkqlIkh1jx9URvCBe5mhOyq+cWRU2Zt4d1M5lfuTH7+gdRgLqn8c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753370614; c=relaxed/simple; bh=Zi6IDDpoS9Ju4hosKorQswwX55xC7wpT4z9/JYXU1E0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=UuSXy7ashf8dYNScWg5gWWLXB8IiEcWP96SXSIqXRFR8/wUYVzcBJ28w+6rxtWeR0sjY9Rz8ugj/WL6+P5l3S1tJzbBA/5OFYObf9gon8PFxPXHcLMWVQFysXfgdOS+Bo61LsNaoRwsVH0KwYY+FOPuaeRSVTuGw9ngZI9okrqc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=AX2TNCo/; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="AX2TNCo/" Received: by smtp.kernel.org (Postfix) with ESMTPS id 47FCEC4CEF1; Thu, 24 Jul 2025 15:23:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1753370614; bh=Zi6IDDpoS9Ju4hosKorQswwX55xC7wpT4z9/JYXU1E0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=AX2TNCo/jocHN41yMdZ2XQpEKXtcdWlaKfHt3yIoTMe6ezJI/+yUi58bvVmHakFrn 0katFrZdEvLf85Fj1p3L16P6Q/Oj9pHsVGfeKAq5PJoV6hlKdL9VBwvrHs/sVSHmxf EhD4k6bkPiz1MWLqD0P7gxXRUooqbxKNMnuj8v+eYhh5PCuAwldugR4mM2dFVsCXj3 JkIbfjzfqGLvPPHb3spruBzKEpvmu83uwqBZFQKzzwBQFAZ3ZzEdCpsNiP3MxqcB8O vKQjZRQdRbrhT/bdN5WkyHgXlPJq5hrOwWRh/2Xjy9jdlMaeYONjnTLNRdLe9L6ZKK 1j6x50ZmieYLg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37D92C83F1A; Thu, 24 Jul 2025 15:23:34 +0000 (UTC) From: Aleksa Paunovic via B4 Relay Date: Thu, 24 Jul 2025 17:23:25 +0200 Subject: [PATCH v5 1/7] dt-bindings: riscv: Add xmipsexectl ISA extension description Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250724-p8700-pause-v5-1-a6cbbe1c3412@htecgroup.com> References: <20250724-p8700-pause-v5-0-a6cbbe1c3412@htecgroup.com> In-Reply-To: <20250724-p8700-pause-v5-0-a6cbbe1c3412@htecgroup.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jonathan Corbet Cc: Palmer Dabbelt , Conor Dooley , Djordje Todorovic , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Aleksa Paunovic , Conor Dooley X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1753370612; l=1355; i=aleksa.paunovic@htecgroup.com; s=20250514; h=from:subject:message-id; bh=YgG7inSQQ5V7j0uCLEwS/5ucVThfyy6CA6ktsQ9XHnU=; b=ptCHQ1B2h5iN8micPgjKEGy82G2w1BNtSjEs+wuE3VlzFKIEvR3Y3DbQuOOLl9ErWfKz1DQSY HJL14K0HuXkCCySBJYtAauAKjFzt6A5oln0zXi1phgvbD4cOfZV2tay X-Developer-Key: i=aleksa.paunovic@htecgroup.com; a=ed25519; pk=gFVSVYLKAgJiS5qCnDyUMGOFuczv8C6o0UmRs+fgisA= X-Endpoint-Received: by B4 Relay for aleksa.paunovic@htecgroup.com/20250514 with auth_id=403 X-Original-From: Aleksa Paunovic Reply-To: aleksa.paunovic@htecgroup.com From: Aleksa Paunovic The xmipsexectl extension is described in the MIPS RV64 P8700/P8700-F Multiprocessing System Programmer=E2=80=99s Guide linked at [1]. Link: https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Referen= ce_Manual_Rev1.84_5-31-2025.pdf Signed-off-by: Aleksa Paunovic Acked-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index ede6a58ccf5347d92785dc085a011052c1aade14..de41a6f074d3af2ceaf5293dfe7= 5d16f43d416d6 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -662,6 +662,12 @@ properties: Registers in the AX45MP datasheet. https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.= 0.0-Datasheet.pdf =20 + # MIPS + - const: xmipsexectl + description: + The MIPS extension for execution control as documented in + https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_= Reference_Manual_Rev1.84_5-31-2025.pdf + # SiFive - const: xsfvqmaccdod description: --=20 2.34.1 From nobody Mon Oct 6 04:56:04 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A66E92E9EB4; Thu, 24 Jul 2025 15:23:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753370614; cv=none; b=gEPt9cHa64nfz52CvHBocJFfxMK99jDg3w0/7lAETL5ddYZEpVHm78C4QnrEKzQvVDqSde1cWJY3k5Zj7KgfBkxFqKE9F9s/qTnQhU5IFrfCLCIuYZcqFnOTKAoAEim7D1SQNgo8oYqA0MOMgnR/09B/Zq4WWnufTAqKsjR67e4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753370614; c=relaxed/simple; bh=SA8CE4M5Qa6UdlIRt+RpmjxjbOkMQl4k3cuHPidEo74=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=DkLPLAl9+1Y7KFi2ulgts9csIGGUcLD0lgGXR2M/gJGfQwhxfo0G7O7bAo8bTmAOPQ6fYzA2KGAxsejjf4j4WQhXrQSIJHqNNGJIsQa+hJRtmbMF5JFAo2T5S9rM3WtuQzEmbkFa4ysOUieuz/ZbGqm/Lv6TFFsI3+3LIIFevjA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=EyXl5icl; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="EyXl5icl" Received: by smtp.kernel.org (Postfix) with ESMTPS id 55964C4CEF6; Thu, 24 Jul 2025 15:23:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1753370614; bh=SA8CE4M5Qa6UdlIRt+RpmjxjbOkMQl4k3cuHPidEo74=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=EyXl5iclKzqNdRCfrpy4bK6u4CYzItl/SKxA0Ssg6WgAGF9ZdvewnxtoueIf5BdUd Ut5BbboWCYMP9pu44NzDt12EOEE4cnhZsUoIotX5U5bWr0N88L7u/JS7WI5CGtoeLd RU/6Z7FXd9ioiSV+3aTXr0SmbT8GeXcxvhj17LRP2gn0FG4AZ6SVeR8gw9vXdLqate 5Ea3zq2huXzaSJJmdruXssHSBnfTY18vpdtHxbX8XIn454i96ZuXHz4Uwvvy2kwzF6 e/RU3Xtln2tOH4+W5I1jirxinz5JpcKBlBIjq9/uvV8Js4d2Ldgp4/pqmpAwBrAXuL p9QpYzhqWHWKw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46104C87FCA; Thu, 24 Jul 2025 15:23:34 +0000 (UTC) From: Aleksa Paunovic via B4 Relay Date: Thu, 24 Jul 2025 17:23:26 +0200 Subject: [PATCH v5 2/7] riscv: Add xmipsexectl as a vendor extension Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250724-p8700-pause-v5-2-a6cbbe1c3412@htecgroup.com> References: <20250724-p8700-pause-v5-0-a6cbbe1c3412@htecgroup.com> In-Reply-To: <20250724-p8700-pause-v5-0-a6cbbe1c3412@htecgroup.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jonathan Corbet Cc: Palmer Dabbelt , Conor Dooley , Djordje Todorovic , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Aleksa Paunovic , Alexandre Ghiti X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1753370612; l=5332; i=aleksa.paunovic@htecgroup.com; s=20250514; h=from:subject:message-id; bh=RxFj25XrnJLQOzustfdJ86PI6vDuIP115iXStW8uyYM=; b=QvK85mZsi5D1m7U3zwqGO+C/+3+ktThhG/OxVQ0N8b3RmGHAGKEcFy9PQ4fQCFxtZJQJBfHog 5zwIkfMb9RfB26/Vp+wDPj7lDDeweR7a1+U+RG7FdILYTpebJ2aJlR7 X-Developer-Key: i=aleksa.paunovic@htecgroup.com; a=ed25519; pk=gFVSVYLKAgJiS5qCnDyUMGOFuczv8C6o0UmRs+fgisA= X-Endpoint-Received: by B4 Relay for aleksa.paunovic@htecgroup.com/20250514 with auth_id=403 X-Original-From: Aleksa Paunovic Reply-To: aleksa.paunovic@htecgroup.com From: Aleksa Paunovic Add support for MIPS vendor extensions. Add support for the xmipsexectl vendor extension. Signed-off-by: Aleksa Paunovic Reviewed-by: Alexandre Ghiti --- arch/riscv/Kconfig.vendor | 13 +++++++++++++ arch/riscv/include/asm/vendor_extensions/mips.h | 18 ++++++++++++++++++ arch/riscv/kernel/vendor_extensions.c | 10 ++++++++++ arch/riscv/kernel/vendor_extensions/Makefile | 1 + arch/riscv/kernel/vendor_extensions/mips.c | 22 ++++++++++++++++++++++ 5 files changed, 64 insertions(+) diff --git a/arch/riscv/Kconfig.vendor b/arch/riscv/Kconfig.vendor index e14f26368963c178e3271e0f716b27fff7671e78..3c1f92e406c3f21481b56e61229= 716fd02ab81b2 100644 --- a/arch/riscv/Kconfig.vendor +++ b/arch/riscv/Kconfig.vendor @@ -16,6 +16,19 @@ config RISCV_ISA_VENDOR_EXT_ANDES If you don't know what to do here, say Y. endmenu =20 +menu "MIPS" +config RISCV_ISA_VENDOR_EXT_MIPS + bool "MIPS vendor extension support" + select RISCV_ISA_VENDOR_EXT + default y + help + Say N here to disable detection of and support for all MIPS vendor + extensions. Without this option enabled, MIPS vendor extensions will + not be detected at boot and their presence not reported to userspace. + + If you don't know what to do here, say Y. +endmenu + menu "SiFive" config RISCV_ISA_VENDOR_EXT_SIFIVE bool "SiFive vendor extension support" diff --git a/arch/riscv/include/asm/vendor_extensions/mips.h b/arch/riscv/i= nclude/asm/vendor_extensions/mips.h new file mode 100644 index 0000000000000000000000000000000000000000..133e55985d827ce7d6057004b59= 0bdcbbdb1ec8c --- /dev/null +++ b/arch/riscv/include/asm/vendor_extensions/mips.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2025 MIPS. + */ + +#ifndef _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_H +#define _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_H + +#include + +#define RISCV_ISA_VENDOR_EXT_XMIPSEXECTL 0 + +#ifndef __ASSEMBLER__ +struct riscv_isa_vendor_ext_data_list; +extern struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_mip= s; +#endif + +#endif // _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_H diff --git a/arch/riscv/kernel/vendor_extensions.c b/arch/riscv/kernel/vend= or_extensions.c index 92d8ff81f42c9ceba63bef0170ab134564a24a4e..bb4a7592368560ebacbcd8a5ce3= 35eea6312ea5c 100644 --- a/arch/riscv/kernel/vendor_extensions.c +++ b/arch/riscv/kernel/vendor_extensions.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include =20 @@ -16,6 +17,9 @@ struct riscv_isa_vendor_ext_data_list *riscv_isa_vendor_e= xt_list[] =3D { #ifdef CONFIG_RISCV_ISA_VENDOR_EXT_ANDES &riscv_isa_vendor_ext_list_andes, #endif +#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_MIPS + &riscv_isa_vendor_ext_list_mips, +#endif #ifdef CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE &riscv_isa_vendor_ext_list_sifive, #endif @@ -49,6 +53,12 @@ bool __riscv_isa_vendor_extension_available(int cpu, uns= igned long vendor, unsig cpu_bmap =3D riscv_isa_vendor_ext_list_andes.per_hart_isa_bitmap; break; #endif + #ifdef CONFIG_RISCV_ISA_VENDOR_EXT_MIPS + case MIPS_VENDOR_ID: + bmap =3D &riscv_isa_vendor_ext_list_mips.all_harts_isa_bitmap; + cpu_bmap =3D riscv_isa_vendor_ext_list_mips.per_hart_isa_bitmap; + break; + #endif #ifdef CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE case SIFIVE_VENDOR_ID: bmap =3D &riscv_isa_vendor_ext_list_sifive.all_harts_isa_bitmap; diff --git a/arch/riscv/kernel/vendor_extensions/Makefile b/arch/riscv/kern= el/vendor_extensions/Makefile index a4eca96d1c8a2fd165220f6439a3884cf90a9593..ccad4ebafb43412e72e654da3bd= b9face53b80c6 100644 --- a/arch/riscv/kernel/vendor_extensions/Makefile +++ b/arch/riscv/kernel/vendor_extensions/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only =20 obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_ANDES) +=3D andes.o +obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_MIPS) +=3D mips.o obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE) +=3D sifive.o obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE) +=3D sifive_hwprobe.o obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD) +=3D thead.o diff --git a/arch/riscv/kernel/vendor_extensions/mips.c b/arch/riscv/kernel= /vendor_extensions/mips.c new file mode 100644 index 0000000000000000000000000000000000000000..f691129f96c21f2ef089124f4b6= 4a6f0a8e6d4aa --- /dev/null +++ b/arch/riscv/kernel/vendor_extensions/mips.c @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025 MIPS. + */ + +#include +#include +#include + +#include +#include +#include + +/* All MIPS vendor extensions supported in Linux */ +static const struct riscv_isa_ext_data riscv_isa_vendor_ext_mips[] =3D { + __RISCV_ISA_EXT_DATA(xmipsexectl, RISCV_ISA_VENDOR_EXT_XMIPSEXECTL), +}; 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Thu, 24 Jul 2025 15:23:34 +0000 (UTC) From: Aleksa Paunovic via B4 Relay Date: Thu, 24 Jul 2025 17:23:27 +0200 Subject: [PATCH v5 3/7] riscv: Add xmipsexectl instructions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250724-p8700-pause-v5-3-a6cbbe1c3412@htecgroup.com> References: <20250724-p8700-pause-v5-0-a6cbbe1c3412@htecgroup.com> In-Reply-To: <20250724-p8700-pause-v5-0-a6cbbe1c3412@htecgroup.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jonathan Corbet Cc: Palmer Dabbelt , Conor Dooley , Djordje Todorovic , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Aleksa Paunovic , Alexandre Ghiti X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1753370612; l=1601; i=aleksa.paunovic@htecgroup.com; s=20250514; h=from:subject:message-id; bh=UiyuNpcwz9mf/w7Z4EE+JWW7TpbY11AARRS/HoJAhyY=; b=kXnwDRLnXwjTZ4lr4Rsy/L+SAr13tjMAbNWyOnuvvm6e4zSvz3YLRNrh0IR7dMh+8xMX09US2 Wwjwe0PaWVDBXThnyVKeFAMlGqY3bEoiyc6llpvBoqixkCM53+F0yMu X-Developer-Key: i=aleksa.paunovic@htecgroup.com; a=ed25519; pk=gFVSVYLKAgJiS5qCnDyUMGOFuczv8C6o0UmRs+fgisA= X-Endpoint-Received: by B4 Relay for aleksa.paunovic@htecgroup.com/20250514 with auth_id=403 X-Original-From: Aleksa Paunovic Reply-To: aleksa.paunovic@htecgroup.com From: Aleksa Paunovic Add xmipsexectl instruction opcodes. This includes the MIPS.PAUSE, MIPS.EHB, and MIPS.IHB instructions. Signed-off-by: Aleksa Paunovic Reviewed-by: Alexandre Ghiti --- arch/riscv/include/asm/vendor_extensions/mips.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/riscv/include/asm/vendor_extensions/mips.h b/arch/riscv/i= nclude/asm/vendor_extensions/mips.h index 133e55985d827ce7d6057004b590bdcbbdb1ec8c..ea8ca747d691df2e9ee7e5360f8= 00fbdccfe3945 100644 --- a/arch/riscv/include/asm/vendor_extensions/mips.h +++ b/arch/riscv/include/asm/vendor_extensions/mips.h @@ -15,4 +15,23 @@ struct riscv_isa_vendor_ext_data_list; extern struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_mip= s; #endif =20 +/* Extension specific instructions */ + +/* + * All of the xmipsexectl extension instructions are + * =E2=80=98hint=E2=80=99 encodings of the SLLI instruction, + * with rd =3D 0, rs1 =3D 0 and imm =3D 1 for IHB, imm =3D 3 for EHB, + * and imm =3D 5 for PAUSE. + * MIPS.PAUSE is an alternative opcode which is implemented to have the + * same behavior as PAUSE on some MIPS RISCV cores. + * MIPS.EHB clears all execution hazards before allowing + * any subsequent instructions to execute. + * MIPS.IHB clears all instruction hazards before + * allowing any subsequent instructions to fetch. + */ + +#define MIPS_PAUSE ".4byte 0x00501013\n\t" +#define MIPS_EHB ".4byte 0x00301013\n\t" +#define MIPS_IHB ".4byte 0x00101013\n\t" + #endif // _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_H --=20 2.34.1 From nobody Mon Oct 6 04:56:04 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B1A262E9EC6; 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pk=gFVSVYLKAgJiS5qCnDyUMGOFuczv8C6o0UmRs+fgisA= X-Endpoint-Received: by B4 Relay for aleksa.paunovic@htecgroup.com/20250514 with auth_id=403 X-Original-From: Aleksa Paunovic Reply-To: aleksa.paunovic@htecgroup.com From: Aleksa Paunovic Add a new hwprobe key "RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0" which allows userspace to probe for the new xmipsexectl vendor extension. Signed-off-by: Aleksa Paunovic Reviewed-by: Alexandre Ghiti --- arch/riscv/include/asm/hwprobe.h | 3 ++- .../include/asm/vendor_extensions/mips_hwprobe.h | 22 ++++++++++++++++++= +++ arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/include/uapi/asm/vendor/mips.h | 3 +++ arch/riscv/kernel/sys_hwprobe.c | 4 ++++ arch/riscv/kernel/vendor_extensions/Makefile | 1 + arch/riscv/kernel/vendor_extensions/mips_hwprobe.c | 23 ++++++++++++++++++= ++++ 7 files changed, 56 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwpr= obe.h index 7fe0a379474ae2c64d300d6fee4a012173f6a6d7..948d2b34e94e84e4c2c351ffe91= f4b3afcefc3f7 100644 --- a/arch/riscv/include/asm/hwprobe.h +++ b/arch/riscv/include/asm/hwprobe.h @@ -8,7 +8,7 @@ =20 #include =20 -#define RISCV_HWPROBE_MAX_KEY 13 +#define RISCV_HWPROBE_MAX_KEY 14 =20 static inline bool riscv_hwprobe_key_is_valid(__s64 key) { @@ -22,6 +22,7 @@ static inline bool hwprobe_key_is_bitmask(__s64 key) case RISCV_HWPROBE_KEY_IMA_EXT_0: case RISCV_HWPROBE_KEY_CPUPERF_0: case RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0: + case RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0: case RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0: return true; } diff --git a/arch/riscv/include/asm/vendor_extensions/mips_hwprobe.h b/arch= /riscv/include/asm/vendor_extensions/mips_hwprobe.h new file mode 100644 index 0000000000000000000000000000000000000000..e63f664b6b1766e5fc3e68fc696= 607bcf3e31776 --- /dev/null +++ b/arch/riscv/include/asm/vendor_extensions/mips_hwprobe.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2025 MIPS. + */ + +#ifndef _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_HWPROBE_H_ +#define _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_HWPROBE_H_ + +#include +#include + +#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_MIPS +void hwprobe_isa_vendor_ext_mips_0(struct riscv_hwprobe *pair, const struc= t cpumask *cpus); +#else +static inline void hwprobe_isa_vendor_ext_mips_0(struct riscv_hwprobe *pai= r, + const struct cpumask *cpus) +{ + pair->value =3D 0; +} +#endif + +#endif // _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_HWPROBE_H_ diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index aaf6ad97049931381f9542bb9316c873ec6ab9f6..5d30a4fae37a82ef4d968d20b18= 7420772ad8946 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -106,6 +106,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0 11 #define RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE 12 #define RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0 13 +#define RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0 14 /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ =20 /* Flags */ diff --git a/arch/riscv/include/uapi/asm/vendor/mips.h b/arch/riscv/include= /uapi/asm/vendor/mips.h new file mode 100644 index 0000000000000000000000000000000000000000..11d41651178233a5f06ab9541ea= 0506d9883aa19 --- /dev/null +++ b/arch/riscv/include/uapi/asm/vendor/mips.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ + +#define RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTL (1 << 0) diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprob= e.c index 3e9259790816e46092d893df6321deaac3dd9795..000f4451a9d873d5f068986a146= 15de3a2a5601d 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -307,6 +308,9 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, case RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0: hwprobe_isa_vendor_ext_thead_0(pair, cpus); break; + case RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0: + hwprobe_isa_vendor_ext_mips_0(pair, cpus); + break; =20 /* * For forward compatibility, unknown keys don't fail the whole diff --git a/arch/riscv/kernel/vendor_extensions/Makefile b/arch/riscv/kern= el/vendor_extensions/Makefile index ccad4ebafb43412e72e654da3bdb9face53b80c6..bf116c82b6bdb3aee23e27fc0b2= a69be7c7a5ccb 100644 --- a/arch/riscv/kernel/vendor_extensions/Makefile +++ b/arch/riscv/kernel/vendor_extensions/Makefile @@ -2,6 +2,7 @@ =20 obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_ANDES) +=3D andes.o obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_MIPS) +=3D mips.o +obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_MIPS) +=3D mips_hwprobe.o obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE) +=3D sifive.o obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE) +=3D sifive_hwprobe.o obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD) +=3D thead.o diff --git a/arch/riscv/kernel/vendor_extensions/mips_hwprobe.c b/arch/risc= v/kernel/vendor_extensions/mips_hwprobe.c new file mode 100644 index 0000000000000000000000000000000000000000..de7aa4a7ff668e18778efcdef77= b994178ca85c3 --- /dev/null +++ b/arch/riscv/kernel/vendor_extensions/mips_hwprobe.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025 MIPS. + */ + +#include +#include +#include +#include + +#include +#include + +#include +#include + +void hwprobe_isa_vendor_ext_mips_0(struct riscv_hwprobe *pair, + const struct cpumask *cpus) +{ + VENDOR_EXTENSION_SUPPORTED( + pair, cpus, riscv_isa_vendor_ext_list_mips.per_hart_isa_bitmap, + { VENDOR_EXT_KEY(XMIPSEXECTL); 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Thu, 24 Jul 2025 15:23:34 +0000 (UTC) From: Aleksa Paunovic via B4 Relay Date: Thu, 24 Jul 2025 17:23:29 +0200 Subject: [PATCH v5 5/7] riscv: hwprobe: Document MIPS xmipsexectl vendor extension Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250724-p8700-pause-v5-5-a6cbbe1c3412@htecgroup.com> References: <20250724-p8700-pause-v5-0-a6cbbe1c3412@htecgroup.com> In-Reply-To: <20250724-p8700-pause-v5-0-a6cbbe1c3412@htecgroup.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jonathan Corbet Cc: Palmer Dabbelt , Conor Dooley , Djordje Todorovic , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Aleksa Paunovic , Alexandre Ghiti X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1753370612; l=1488; i=aleksa.paunovic@htecgroup.com; s=20250514; h=from:subject:message-id; bh=+gPZ/fNoQiSSWPCUqLgBumEM1NqDdXrfNQZR7V7bk6c=; b=0ws0HFUQbx/6OicMmxR4Fty6PTdRa5VPTDzN+7p1L2+GXfXmDi0Cglc+Jz2IZhzthF5KpPaYr V7ZHPYn1xI0BJSotFQJm8XlvfzYKVQ6AJQ96cK8EJk1zAMVm1SCIj2Q X-Developer-Key: i=aleksa.paunovic@htecgroup.com; a=ed25519; pk=gFVSVYLKAgJiS5qCnDyUMGOFuczv8C6o0UmRs+fgisA= X-Endpoint-Received: by B4 Relay for aleksa.paunovic@htecgroup.com/20250514 with auth_id=403 X-Original-From: Aleksa Paunovic Reply-To: aleksa.paunovic@htecgroup.com From: Aleksa Paunovic Document support for MIPS vendor extensions using the key "RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0" and xmipsexectl vendor extension using the key "RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTL". Signed-off-by: Aleksa Paunovic Reviewed-by: Alexandre Ghiti --- Documentation/arch/riscv/hwprobe.rst | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/risc= v/hwprobe.rst index 2aa9be272d5de1c15559a978a956bc36c34de81c..2f449c9b15bdd6b9813c9a968de= ca1a4c4ff9b14 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -327,6 +327,15 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED`: Misaligned vec= tor accesses are not supported at all and will generate a misaligned address fault. =20 +* :c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0`: A bitmask containing the + mips vendor extensions that are compatible with the + :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior. + + * MIPS + + * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTL`: The xmipsexectl ven= dor + extension is supported in the MIPS ISA extensions spec. + * :c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0`: A bitmask containing the thead vendor extensions that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior. --=20 2.34.1 From nobody Mon Oct 6 04:56:04 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 073502EA75A; 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Signed-off-by: Aleksa Paunovic Reviewed-by: Alexandre Ghiti --- tools/arch/riscv/include/asm/vdso/processor.h | 27 +++++++++++++++++------= ---- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/tools/arch/riscv/include/asm/vdso/processor.h b/tools/arch/ris= cv/include/asm/vdso/processor.h index 0665b117f30f2766a23446fbd7c8ce82d1843a93..b089d4be998f4ab7bc43a96496a= 6c6f1bb38da4d 100644 --- a/tools/arch/riscv/include/asm/vdso/processor.h +++ b/tools/arch/riscv/include/asm/vdso/processor.h @@ -4,26 +4,33 @@ =20 #ifndef __ASSEMBLER__ =20 +#include +#include +#include +#include #include =20 static inline void cpu_relax(void) { + struct riscv_hwprobe pair; + bool has_mipspause; #ifdef __riscv_muldiv int dummy; /* In lieu of a halt instruction, induce a long-latency stall. */ __asm__ __volatile__ ("div %0, %0, zero" : "=3Dr" (dummy)); #endif =20 -#ifdef CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE - /* - * Reduce instruction retirement. - * This assumes the PC changes. - */ - __asm__ __volatile__ ("pause"); -#else - /* Encoding of the pause instruction */ - __asm__ __volatile__ (".4byte 0x100000F"); -#endif + pair.key =3D RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0; + __riscv_hwprobe(&pair, 1, 0, NULL, 0); + has_mipspause =3D pair.value & RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTL; + + if (has_mipspause) { + __asm__ __volatile__(MIPS_PAUSE); + } else { + /* Encoding of the pause instruction */ + __asm__ __volatile__(".4byte 0x100000F"); + } + barrier(); } =20 --=20 2.34.1 From nobody Mon Oct 6 04:56:04 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 074402EAB61; Thu, 24 Jul 2025 15:23:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753370615; cv=none; b=PDc0vDvjYCp9gY+iEGcVSOXRisy1XoM02AHGVC7Cb6UZwqyDiZ5z7KkZcb3S//Bw/ocDS9VkNpLnDmOuNQiM20b+EHTR40zug2EWqNzXz4sLQVIhYqWSb8QNabo92t8KxYWIsFGV38fefNAGLzbSe02Gl6k1jvnOTQp+LQbnb4c= ARC-Message-Signature: i=1; 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b=bhwJw7LSclMf4Crhgi2x+Cmv29LYNTzzyZTUnUmNJRjEE9+191qYlZ4QBZxWLN3qo Gzbaw/+SHw9RLmqro5f7/GHhewqQZDU/7F0KCFujWsf/C9CYGqQcMkVfZoqOkYTVTo LWCY3Nx2q/cp7UUHD5sLpFEYRvfosOfGVBEl3cHBk8M5bl4uJMRKkSXbyMnCjbETF9 XPQCQEk6bhiS6CTw/mhTlvLIjZOph1uFw5bwOOmIA9yKeqAp3TbfkrS/lUOp3+nF3N R0xaMzLtzLst2/f1T3r0ryuYGuVlknU0xnVJcOLoZAoO4rE9MOvTxUFQUSZ/Na86H5 Z6l5tT8bTIl4Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C2BDC87FCA; Thu, 24 Jul 2025 15:23:34 +0000 (UTC) From: Aleksa Paunovic via B4 Relay Date: Thu, 24 Jul 2025 17:23:31 +0200 Subject: [PATCH v5 7/7] riscv: errata: Fix the PAUSE Opcode for MIPS P8700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250724-p8700-pause-v5-7-a6cbbe1c3412@htecgroup.com> References: <20250724-p8700-pause-v5-0-a6cbbe1c3412@htecgroup.com> In-Reply-To: <20250724-p8700-pause-v5-0-a6cbbe1c3412@htecgroup.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jonathan Corbet Cc: Palmer Dabbelt , Conor Dooley , Djordje Todorovic , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Aleksa Paunovic , Aleksandar Rikalo , Raj Vishwanathan4 , Alexandre Ghiti X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1753370612; l=10604; i=aleksa.paunovic@htecgroup.com; s=20250514; h=from:subject:message-id; bh=ec9KHfCdvJydLARTt0talwBD+mHGsJuBleTVx2zquUg=; b=WMTAsU0dQRUaD7Gfro+7hCxjIapJvTChI4LrjtPBTO6xlAe9f5QZlQD6EiEL3wEIXQ6745sZC Hi0Bi+jeYMDC1Pgd9CfOCfts6ZBnYQZnqnkqJXSoG3K2S6+dcetgsrL X-Developer-Key: i=aleksa.paunovic@htecgroup.com; a=ed25519; pk=gFVSVYLKAgJiS5qCnDyUMGOFuczv8C6o0UmRs+fgisA= X-Endpoint-Received: by B4 Relay for aleksa.paunovic@htecgroup.com/20250514 with auth_id=403 X-Original-From: Aleksa Paunovic Reply-To: aleksa.paunovic@htecgroup.com From: Djordje Todorovic Add ERRATA_MIPS and ERRATA_MIPS_P8700_PAUSE_OPCODE configs. Handle errata for the MIPS PAUSE instruction. Signed-off-by: Djordje Todorovic Signed-off-by: Aleksandar Rikalo Signed-off-by: Raj Vishwanathan4 Signed-off-by: Aleksa Paunovic Reviewed-by: Alexandre Ghiti --- arch/riscv/Kconfig.errata | 23 ++++++++++ arch/riscv/errata/Makefile | 1 + arch/riscv/errata/mips/Makefile | 5 +++ arch/riscv/errata/mips/errata.c | 67 ++++++++++++++++++++++++= ++++ arch/riscv/include/asm/alternative.h | 3 ++ arch/riscv/include/asm/cmpxchg.h | 3 +- arch/riscv/include/asm/errata_list.h | 13 +++++- arch/riscv/include/asm/errata_list_vendors.h | 5 +++ arch/riscv/include/asm/vdso/processor.h | 3 +- arch/riscv/include/asm/vendorid_list.h | 1 + arch/riscv/kernel/alternative.c | 5 +++ arch/riscv/mm/init.c | 1 + 12 files changed, 127 insertions(+), 3 deletions(-) diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata index d2c982ba5373041a2d680f7fd5bced6d98357bdd..ac64123433e717d3cd4a6d107f1= 328d27297f9cc 100644 --- a/arch/riscv/Kconfig.errata +++ b/arch/riscv/Kconfig.errata @@ -21,6 +21,29 @@ config ERRATA_ANDES_CMO =20 If you don't know what to do here, say "Y". =20 +config ERRATA_MIPS + bool "MIPS errata" + depends on RISCV_ALTERNATIVE + help + All MIPS errata Kconfig depend on this Kconfig. Disabling + this Kconfig will disable all MIPS errata. Please say "Y" + here if your platform uses MIPS CPU cores. + + Otherwise, please say "N" here to avoid unnecessary overhead. + +config ERRATA_MIPS_P8700_PAUSE_OPCODE + bool "Fix the PAUSE Opcode for MIPS P8700" + depends on ERRATA_MIPS && 64BIT + default n + help + The RISCV MIPS P8700 uses a different opcode for PAUSE. + It is a 'hint' encoding of the SLLI instruction, + with rd=3D0, rs1=3D0 and imm=3D5. It will behave as a NOP + instruction if no additional behavior beyond that of + SLLI is implemented. + + If you are not using the P8700 processor, say n. + config ERRATA_SIFIVE bool "SiFive errata" depends on RISCV_ALTERNATIVE diff --git a/arch/riscv/errata/Makefile b/arch/riscv/errata/Makefile index bc6c77ba837d2da4c98dabab18083d27f46629c7..02a7a3335b1d557933e04cd6d0c= f7bf4260b8c40 100644 --- a/arch/riscv/errata/Makefile +++ b/arch/riscv/errata/Makefile @@ -13,5 +13,6 @@ endif endif =20 obj-$(CONFIG_ERRATA_ANDES) +=3D andes/ +obj-$(CONFIG_ERRATA_MIPS) +=3D mips/ obj-$(CONFIG_ERRATA_SIFIVE) +=3D sifive/ obj-$(CONFIG_ERRATA_THEAD) +=3D thead/ diff --git a/arch/riscv/errata/mips/Makefile b/arch/riscv/errata/mips/Makef= ile new file mode 100644 index 0000000000000000000000000000000000000000..6278c389b801ee6e54e808c80e6= e236c026329c7 --- /dev/null +++ b/arch/riscv/errata/mips/Makefile @@ -0,0 +1,5 @@ +ifdef CONFIG_RISCV_ALTERNATIVE_EARLY +CFLAGS_errata.o :=3D -mcmodel=3Dmedany +endif + +obj-y +=3D errata.o diff --git a/arch/riscv/errata/mips/errata.c b/arch/riscv/errata/mips/errat= a.c new file mode 100644 index 0000000000000000000000000000000000000000..e984a8152208c34690f89d81015= 71b097485c360 --- /dev/null +++ b/arch/riscv/errata/mips/errata.c @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025 MIPS. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static inline bool errata_probe_pause(void) +{ + if (!IS_ENABLED(CONFIG_ERRATA_MIPS_P8700_PAUSE_OPCODE)) + return false; + + if (!riscv_isa_vendor_extension_available(MIPS_VENDOR_ID, XMIPSEXECTL)) + return false; + + return true; +} + +static u32 mips_errata_probe(void) +{ + u32 cpu_req_errata =3D 0; + + if (errata_probe_pause()) + cpu_req_errata |=3D BIT(ERRATA_MIPS_P8700_PAUSE_OPCODE); + + return cpu_req_errata; +} + +void mips_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, + unsigned long archid, unsigned long impid, + unsigned int stage) +{ + struct alt_entry *alt; + u32 cpu_req_errata =3D mips_errata_probe(); + u32 tmp; + + BUILD_BUG_ON(ERRATA_MIPS_NUMBER >=3D RISCV_VENDOR_EXT_ALTERNATIVES_BASE); + + if (stage =3D=3D RISCV_ALTERNATIVES_EARLY_BOOT) + return; + + for (alt =3D begin; alt < end; alt++) { + if (alt->vendor_id !=3D MIPS_VENDOR_ID) + continue; + + if (alt->patch_id >=3D ERRATA_MIPS_NUMBER) { + WARN(1, "MIPS errata id:%d not in kernel errata list\n", + alt->patch_id); + continue; + } + + tmp =3D (1U << alt->patch_id); + if (cpu_req_errata && tmp) { + mutex_lock(&text_mutex); + patch_text_nosync(ALT_OLD_PTR(alt), ALT_ALT_PTR(alt), + alt->alt_len); + mutex_unlock(&text_mutex); + } + } +} diff --git a/arch/riscv/include/asm/alternative.h b/arch/riscv/include/asm/= alternative.h index 0e95539ba451ba55abb15ee4a26b6125c9d0261a..82eabf9a117a864a473a3c916b6= 7bd91d1309671 100644 --- a/arch/riscv/include/asm/alternative.h +++ b/arch/riscv/include/asm/alternative.h @@ -48,6 +48,9 @@ struct alt_entry { void andes_errata_patch_func(struct alt_entry *begin, struct alt_entry *en= d, unsigned long archid, unsigned long impid, unsigned int stage); +void mips_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, + unsigned long archid, unsigned long impid, + unsigned int stage); void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *e= nd, unsigned long archid, unsigned long impid, unsigned int stage); diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpx= chg.h index 0b749e7102162477432f7cf9a34768fbdf2e8cc7..80bd52363c68690f33bfd54e0cc= 40399cd60b57b 100644 --- a/arch/riscv/include/asm/cmpxchg.h +++ b/arch/riscv/include/asm/cmpxchg.h @@ -14,6 +14,7 @@ #include #include #include +#include =20 #define __arch_xchg_masked(sc_sfx, swap_sfx, prepend, sc_append, \ swap_append, r, p, n) \ @@ -438,7 +439,7 @@ static __always_inline void __cmpwait(volatile void *pt= r, return; =20 no_zawrs: - asm volatile(RISCV_PAUSE : : : "memory"); + ALT_RISCV_PAUSE(); } =20 #define __cmpwait_relaxed(ptr, val) \ diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/= errata_list.h index a2481f14b68d56b3435d160793699002a45472eb..6694b5ccdcf85cfe7e767ea4de9= 81b34f2b17b04 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -5,12 +5,12 @@ #ifndef ASM_ERRATA_LIST_H #define ASM_ERRATA_LIST_H =20 -#include #include #include #include #include #include +#include =20 #ifdef __ASSEMBLER__ =20 @@ -42,6 +42,17 @@ asm(ALTERNATIVE("sfence.vma %0, %1", "sfence.vma", SIFIV= E_VENDOR_ID, \ ERRATA_SIFIVE_CIP_1200, CONFIG_ERRATA_SIFIVE_CIP_1200) \ : : "r" (addr), "r" (asid) : "memory") =20 +#define ALT_RISCV_PAUSE() \ +asm(ALTERNATIVE( \ + RISCV_PAUSE, /* Original RISC=E2=80=91V pause insn */ \ + MIPS_PAUSE, /* Replacement for MIPS P8700 */ \ + MIPS_VENDOR_ID, /* Vendor ID to match */ \ + ERRATA_MIPS_P8700_PAUSE_OPCODE, /* patch_id */ \ + CONFIG_ERRATA_MIPS_P8700_PAUSE_OPCODE) \ + : /* no outputs */ \ + : /* no inputs */ \ + : "memory") + /* * _val is marked as "will be overwritten", so need to set it to 0 * in the default case. diff --git a/arch/riscv/include/asm/errata_list_vendors.h b/arch/riscv/incl= ude/asm/errata_list_vendors.h index a7473cb8874d62b26ae5c6a2c06144b922e24efe..9739a70ed69984ba4fc5f51a496= 7a58c4b02613a 100644 --- a/arch/riscv/include/asm/errata_list_vendors.h +++ b/arch/riscv/include/asm/errata_list_vendors.h @@ -22,4 +22,9 @@ #define ERRATA_THEAD_NUMBER 4 #endif =20 +#ifdef CONFIG_ERRATA_MIPS +#define ERRATA_MIPS_P8700_PAUSE_OPCODE 0 +#define ERRATA_MIPS_NUMBER 1 +#endif + #endif diff --git a/arch/riscv/include/asm/vdso/processor.h b/arch/riscv/include/a= sm/vdso/processor.h index 98fb44336c055f1c60899cb25c99f2416184c466..c42f95dc8811d8a949898f73381= 51dcc4e987372 100644 --- a/arch/riscv/include/asm/vdso/processor.h +++ b/arch/riscv/include/asm/vdso/processor.h @@ -5,6 +5,7 @@ #ifndef __ASSEMBLER__ =20 #include +#include #include =20 static inline void cpu_relax(void) @@ -19,7 +20,7 @@ static inline void cpu_relax(void) * Reduce instruction retirement. * This assumes the PC changes. */ - __asm__ __volatile__ (RISCV_PAUSE); + ALT_RISCV_PAUSE(); barrier(); } =20 diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/as= m/vendorid_list.h index a5150cdf34d87f01baf6d3ef843bc2d6d8d54095..3b09874d7a6dfb8f8aa45b0be41= c20711d539e78 100644 --- a/arch/riscv/include/asm/vendorid_list.h +++ b/arch/riscv/include/asm/vendorid_list.h @@ -9,5 +9,6 @@ #define MICROCHIP_VENDOR_ID 0x029 #define SIFIVE_VENDOR_ID 0x489 #define THEAD_VENDOR_ID 0x5b7 +#define MIPS_VENDOR_ID 0x722 =20 #endif diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternativ= e.c index 7eb3cb1215c62130c63a72fc650cddff6bae62af..7642704c7f1841f67fc23738063= f22b4ecf58194 100644 --- a/arch/riscv/kernel/alternative.c +++ b/arch/riscv/kernel/alternative.c @@ -47,6 +47,11 @@ static void riscv_fill_cpu_mfr_info(struct cpu_manufactu= rer_info_t *cpu_mfr_info cpu_mfr_info->patch_func =3D andes_errata_patch_func; break; #endif +#ifdef CONFIG_ERRATA_MIPS + case MIPS_VENDOR_ID: + cpu_mfr_info->patch_func =3D mips_errata_patch_func; + break; +#endif #ifdef CONFIG_ERRATA_SIFIVE case SIFIVE_VENDOR_ID: cpu_mfr_info->patch_func =3D sifive_errata_patch_func; diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c index 8d0374d7ce8ed72320f58e4cea212d0e2bce8fd4..3c2293bdfbccfde21c44497504c= 66fc4017f45a9 100644 --- a/arch/riscv/mm/init.c +++ b/arch/riscv/mm/init.c @@ -23,6 +23,7 @@ #include #include =20 +#include #include #include #include --=20 2.34.1