Rockchip RK3528 has one USB 3.0 DWC3 controller, a USB 2.0 EHCI/OHCI
controller and uses a USB2PHY for USB 2.0. The DWC3 controller may also
use the Naneng Combo PHY for USB3.
Add device tree nodes to describe these USB controllers along with the
USB 2.0 PHYs.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
The DWC3 node does not contain any default phys because out of current
and pending supported boards only one board, ROCK 2A, can use USB3.
Remaining boards use the Naneng Combo PHY for PCIe instead of USB3.
---
arch/arm64/boot/dts/rockchip/rk3528.dtsi | 76 ++++++++++++++++++++++++
1 file changed, 76 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
index 85bc3f5aa2c7..3e51a3f51e05 100644
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -243,6 +243,29 @@ soc {
#address-cells = <2>;
#size-cells = <2>;
+ usb_host0_xhci: usb@fe500000 {
+ compatible = "rockchip,rk3528-dwc3", "snps,dwc3";
+ reg = <0x0 0xfe500000 0x0 0x400000>;
+ clocks = <&cru CLK_REF_USB3OTG>,
+ <&cru CLK_SUSPEND_USB3OTG>,
+ <&cru ACLK_USB3OTG>;
+ clock-names = "ref_clk", "suspend_clk", "bus_clk";
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&power RK3528_PD_VPU>;
+ resets = <&cru SRST_A_USB3OTG>;
+ dr_mode = "otg";
+ phy_type = "utmi_wide";
+ snps,dis_enblslpm_quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,dis-tx-ipgap-linecheck-quirk;
+ snps,dis-u1-entry-quirk;
+ snps,dis-u2-entry-quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,parkmode-disable-hs-quirk;
+ snps,parkmode-disable-ss-quirk;
+ status = "disabled";
+ };
+
gic: interrupt-controller@fed01000 {
compatible = "arm,gic-400";
reg = <0x0 0xfed01000 0 0x1000>,
@@ -256,6 +279,30 @@ gic: interrupt-controller@fed01000 {
#interrupt-cells = <3>;
};
+ usb_host0_ehci: usb@ff100000 {
+ compatible = "generic-ehci";
+ reg = <0x0 0xff100000 0x0 0x40000>;
+ clocks = <&cru HCLK_USBHOST>, <&cru HCLK_USBHOST_ARB>,
+ <&u2phy>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&u2phy_host>;
+ phy-names = "usb";
+ power-domains = <&power RK3528_PD_VO>;
+ status = "disabled";
+ };
+
+ usb_host0_ohci: usb@ff140000 {
+ compatible = "generic-ohci";
+ reg = <0x0 0xff140000 0x0 0x40000>;
+ clocks = <&cru HCLK_USBHOST>, <&cru HCLK_USBHOST_ARB>,
+ <&u2phy>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&u2phy_host>;
+ phy-names = "usb";
+ power-domains = <&power RK3528_PD_VO>;
+ status = "disabled";
+ };
+
qos_crypto_a: qos@ff200000 {
compatible = "rockchip,rk3528-qos", "syscon";
reg = <0x0 0xff200000 0x0 0x20>;
@@ -1109,6 +1156,35 @@ dmac: dma-controller@ffd60000 {
#dma-cells = <1>;
arm,pl330-periph-burst;
};
+
+ u2phy: usb2phy@ffdf0000 {
+ compatible = "rockchip,rk3528-usb2phy";
+ reg = <0x0 0xffdf0000 0x0 0x10000>;
+ clocks = <&cru CLK_REF_USBPHY>, <&cru PCLK_USBPHY>;
+ clock-names = "phyclk", "pclk";
+ #clock-cells = <0>;
+ clock-output-names = "clk_usbphy_480m";
+ power-domains = <&power RK3528_PD_VO>;
+ rockchip,usbgrf = <&vo_grf>;
+ status = "disabled";
+
+ u2phy_otg: otg-port {
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "otg-bvalid", "otg-id",
+ "linestate";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ u2phy_host: host-port {
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "linestate";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
};
};
--
2.50.1Hi,
> The DWC3 node does not contain any default phys because out of current
> and pending supported boards only one board, ROCK 2A, can use USB3.
> Remaining boards use the Naneng Combo PHY for PCIe instead of USB3.
I have other RK3528 boards with USB3 and can test this in a few days.
Or do you think that usb3-phy should be added in the dts of the device?
> diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> index 85bc3f5aa2c7..3e51a3f51e05 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> @@ -243,6 +243,29 @@ soc {
> #address-cells = <2>;
> #size-cells = <2>;
>
> + usb_host0_xhci: usb@fe500000 {
> + compatible = "rockchip,rk3528-dwc3", "snps,dwc3";
> + reg = <0x0 0xfe500000 0x0 0x400000>;
> + clocks = <&cru CLK_REF_USB3OTG>,
> + <&cru CLK_SUSPEND_USB3OTG>,
> + <&cru ACLK_USB3OTG>;
> + clock-names = "ref_clk", "suspend_clk", "bus_clk";
> + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&power RK3528_PD_VPU>;
> + resets = <&cru SRST_A_USB3OTG>;
> + dr_mode = "otg";
> + phy_type = "utmi_wide";
> + snps,dis_enblslpm_quirk;
> + snps,dis-del-phy-power-chg-quirk;
> + snps,dis-tx-ipgap-linecheck-quirk;
> + snps,dis-u1-entry-quirk;
> + snps,dis-u2-entry-quirk;
> + snps,dis-u2-freeclk-exists-quirk;
> + snps,parkmode-disable-hs-quirk;
> + snps,parkmode-disable-ss-quirk;
Maybe "snps,dis_u2_susphy_quirk" is needed?
Downstream kernels add this on USB2.0 only devices:
https://github.com/rockchip-linux/kernel/blob/develop-5.10/arch/arm64/boot/dts/rockchip/rk3528-demo.dtsi#L474
> + u2phy: usb2phy@ffdf0000 {
> + u2phy_otg: otg-port {
> + u2phy_host: host-port {
I think it would be better to call it usb2phy, usb2phy0_otg and usb2phy0_host?
In this way, we can put these USB nodes close together in the device's dts.
--
2.25.1
Hi Chukun,
On 7/23/2025 4:30 PM, Chukun Pan wrote:
> Hi,
>
>> The DWC3 node does not contain any default phys because out of current
>> and pending supported boards only one board, ROCK 2A, can use USB3.
>> Remaining boards use the Naneng Combo PHY for PCIe instead of USB3.
>
> I have other RK3528 boards with USB3 and can test this in a few days.
> Or do you think that usb3-phy should be added in the dts of the device?
That is what I did for ROCK 2A testing I added the usb3-phy to the board
dts. Mostly for two reasons, first because I did not want to make this
series fully depend on the naneng-combphy series. And secondly because
the ROCK 2A also have some sort of GPIO controlled mux for USB3 and PCIe
signals that may affect how usb3 support is described in the device tree.
I am open to ideas on how or what default phys to include in soc dtsi.
For the ROCK 2A usb3-phy example, please see the commit "arm64: dts:
rockchip: Enable USB 3.0 port on ROCK 2A" at [1].
[1] https://github.com/Kwiboo/linux-rockchip/commits/next-20250722-rk3528/
>
>> diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
>> index 85bc3f5aa2c7..3e51a3f51e05 100644
>> --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
>> +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
>> @@ -243,6 +243,29 @@ soc {
>> #address-cells = <2>;
>> #size-cells = <2>;
>>
>> + usb_host0_xhci: usb@fe500000 {
>> + compatible = "rockchip,rk3528-dwc3", "snps,dwc3";
>> + reg = <0x0 0xfe500000 0x0 0x400000>;
>> + clocks = <&cru CLK_REF_USB3OTG>,
>> + <&cru CLK_SUSPEND_USB3OTG>,
>> + <&cru ACLK_USB3OTG>;
>> + clock-names = "ref_clk", "suspend_clk", "bus_clk";
>> + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
>> + power-domains = <&power RK3528_PD_VPU>;
>> + resets = <&cru SRST_A_USB3OTG>;
>> + dr_mode = "otg";
>> + phy_type = "utmi_wide";
>> + snps,dis_enblslpm_quirk;
>> + snps,dis-del-phy-power-chg-quirk;
>> + snps,dis-tx-ipgap-linecheck-quirk;
>> + snps,dis-u1-entry-quirk;
>> + snps,dis-u2-entry-quirk;
>> + snps,dis-u2-freeclk-exists-quirk;
>> + snps,parkmode-disable-hs-quirk;
>> + snps,parkmode-disable-ss-quirk;
>
> Maybe "snps,dis_u2_susphy_quirk" is needed?
Maybe, it did not seem to be needed when I tested USB2.0 only or USB3.0,
will run some more tests on my boards.
Any issues you know that snps,dis_u2_susphy_quirk would help fix?
For my latest USB testing I have included a few USB related changes in
U-Boot, e.g. early disable of U3 port. Will push and updated rk3528
branch [2] once source.denx.de is fully back online again.
[2] https://source.denx.de/u-boot/contributors/kwiboo/u-boot/-/commits/rk3528
> Downstream kernels add this on USB2.0 only devices:
> https://github.com/rockchip-linux/kernel/blob/develop-5.10/arch/arm64/boot/dts/rockchip/rk3528-demo.dtsi#L474
>
>> + u2phy: usb2phy@ffdf0000 {
>> + u2phy_otg: otg-port {
>> + u2phy_host: host-port {
>
> I think it would be better to call it usb2phy, usb2phy0_otg and usb2phy0_host?
> In this way, we can put these USB nodes close together in the device's dts.
From what I could see these nodes are named u2phy for 8 other Rockchip
SoCs and only named usb2phy for 3. So I went with what the majority seem
to be calling them.
I fully understand wanting to sort them closer, however we also have the
forthcoming combphy for USB3 that also will be sorted away from the usb
controller nodes. Hopefully someone more can chime in on node naming
suggestions :-)
Regards,
Jonas
>
> --
> 2.25.1
>
>
Hi,
> That is what I did for ROCK 2A testing I added the usb3-phy to the board
> dts. Mostly for two reasons, first because I did not want to make this
> series fully depend on the naneng-combphy series. And secondly because
> the ROCK 2A also have some sort of GPIO controlled mux for USB3 and PCIe
> signals that may affect how usb3 support is described in the device tree.
I tested this on a rk3528 board (usb3 only) with a usb hub:
~# lsusb -t
/: Bus 001.Port 001: Dev 001, Class=root_hub, Driver=xhci-hcd/1p, 480M
|__ Port 001: Dev 002, If 0, Class=[unknown], Driver=hub/4p, 480M
/: Bus 002.Port 001: Dev 001, Class=root_hub, Driver=xhci-hcd/1p, 5000M
|__ Port 001: Dev 002, If 0, Class=[unknown], Driver=hub/4p, 5000M
|__ Port 002: Dev 003, If 0, Class=[unknown], Driver=usb-storage, 5000M
/: Bus 003.Port 001: Dev 001, Class=root_hub, Driver=ehci-platform/1p, 480M
/: Bus 004.Port 001: Dev 001, Class=root_hub, Driver=ohci-platform/1p, 12M
> I am open to ideas on how or what default phys to include in soc dtsi.
I have no problem with this, either is fine.
> > Maybe "snps,dis_u2_susphy_quirk" is needed?
>
> Maybe, it did not seem to be needed when I tested USB2.0 only or USB3.0,
> will run some more tests on my boards.
>
> Any issues you know that snps,dis_u2_susphy_quirk would help fix?
This appears to be to allow the DWC3 core to reliably detect the Vbus
status of the connected PHY. Not sure if this is really needed.
> From what I could see these nodes are named u2phy for 8 other Rockchip
> SoCs and only named usb2phy for 3. So I went with what the majority seem
> to be calling them.
The name u2phy comes from the downstream BSP, and I think it doesn't hurt
to call it usb2phy.
Thanks,
Chukun
--
2.25.1
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