gcc_aux_clk is used in PCIe RC and it is not required in pcie phy, in
pcie phy it should be gcc_phy_aux_clk, so remove gcc_aux_clk and
replace it with gcc_phy_aux_clk.
Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 28 +++++++++++++++------------
1 file changed, 16 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 9997a29901f5..39a4f59d8925 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -7707,16 +7707,18 @@ pcie0_phy: phy@1c04000 {
compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy";
reg = <0x0 0x1c04000 0x0 0x2000>;
- clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+ clocks = <&gcc GCC_PCIE_0_PHY_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_CLKREF_EN>,
<&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
<&gcc GCC_PCIE_0_PIPE_CLK>,
- <&gcc GCC_PCIE_0_PIPEDIV2_CLK>,
- <&gcc GCC_PCIE_0_PHY_AUX_CLK>;
-
- clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe",
- "pipediv2", "phy_aux";
+ <&gcc GCC_PCIE_0_PIPEDIV2_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "rchng",
+ "pipe",
+ "pipediv2";
assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
assigned-clock-rates = <100000000>;
@@ -7873,16 +7875,18 @@ pcie1_phy: phy@1c14000 {
compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy";
reg = <0x0 0x1c14000 0x0 0x4000>;
- clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
+ clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
<&gcc GCC_PCIE_CLKREF_EN>,
<&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
<&gcc GCC_PCIE_1_PIPE_CLK>,
- <&gcc GCC_PCIE_1_PIPEDIV2_CLK>,
- <&gcc GCC_PCIE_1_PHY_AUX_CLK>;
-
- clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe",
- "pipediv2", "phy_aux";
+ <&gcc GCC_PCIE_1_PIPEDIV2_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "rchng",
+ "pipe",
+ "pipediv2";
assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
assigned-clock-rates = <100000000>;
--
2.34.1On Fri, Jul 18, 2025 at 04:17:17PM +0800, Ziyue Zhang wrote: > gcc_aux_clk is used in PCIe RC and it is not required in pcie phy, in > pcie phy it should be gcc_phy_aux_clk, so remove gcc_aux_clk and > replace it with gcc_phy_aux_clk. Expanding on why this is a correct change would be good since this does not yet seem to have been fully resolved: https://lore.kernel.org/lkml/98088092-1987-41cc-ab70-c9a5d3fdbb41@oss.qualcomm.com/ Looks like you're missing a Fixes tag here too. > Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com> Johan
On 7/18/25 12:02 PM, Johan Hovold wrote:
> On Fri, Jul 18, 2025 at 04:17:17PM +0800, Ziyue Zhang wrote:
>> gcc_aux_clk is used in PCIe RC and it is not required in pcie phy, in
>> pcie phy it should be gcc_phy_aux_clk, so remove gcc_aux_clk and
>> replace it with gcc_phy_aux_clk.
>
> Expanding on why this is a correct change would be good since this does
> not yet seem to have been fully resolved:
>
> https://lore.kernel.org/lkml/98088092-1987-41cc-ab70-c9a5d3fdbb41@oss.qualcomm.com/
I dug out some deep memories and recalled that _PHY_AUX_CLK was
necessary on x1e for the Gen4 PHY to initialize properly. This
can be easily reproduced:
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index a9a7bb676c6f..d5ef6bef2b23 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -3312,7 +3312,7 @@ pcie3_phy: phy@1be0000 {
compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy";
reg = <0 0x01be0000 0 0x10000>;
- clocks = <&gcc GCC_PCIE_3_PHY_AUX_CLK>,
+ clocks = <&gcc GCC_PCIE_3_AUX_CLK>,
<&gcc GCC_PCIE_3_CFG_AHB_CLK>,
<&tcsr TCSR_PCIE_8L_CLKREF_EN>,
<&gcc GCC_PCIE_3_PHY_RCHNG_CLK>,
==>
[ 6.967231] qcom-qmp-pcie-phy 1be0000.phy: phy initialization timed-out
[ 6.974462] phy phy-1be0000.phy.0: phy poweron failed --> -110
And the (non-PHY_)AUX_CLK is necessary for at least one of them, as
removing it causes a crash on boot
Konrad
On 7/18/2025 6:53 PM, Konrad Dybcio wrote:
> On 7/18/25 12:02 PM, Johan Hovold wrote:
>> On Fri, Jul 18, 2025 at 04:17:17PM +0800, Ziyue Zhang wrote:
>>> gcc_aux_clk is used in PCIe RC and it is not required in pcie phy, in
>>> pcie phy it should be gcc_phy_aux_clk, so remove gcc_aux_clk and
>>> replace it with gcc_phy_aux_clk.
>> Expanding on why this is a correct change would be good since this does
>> not yet seem to have been fully resolved:
>>
>> https://lore.kernel.org/lkml/98088092-1987-41cc-ab70-c9a5d3fdbb41@oss.qualcomm.com/
> I dug out some deep memories and recalled that _PHY_AUX_CLK was
> necessary on x1e for the Gen4 PHY to initialize properly. This
> can be easily reproduced:
>
> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> index a9a7bb676c6f..d5ef6bef2b23 100644
> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> @@ -3312,7 +3312,7 @@ pcie3_phy: phy@1be0000 {
> compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy";
> reg = <0 0x01be0000 0 0x10000>;
>
> - clocks = <&gcc GCC_PCIE_3_PHY_AUX_CLK>,
> + clocks = <&gcc GCC_PCIE_3_AUX_CLK>,
> <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
> <&tcsr TCSR_PCIE_8L_CLKREF_EN>,
> <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>,
>
> ==>
> [ 6.967231] qcom-qmp-pcie-phy 1be0000.phy: phy initialization timed-out
> [ 6.974462] phy phy-1be0000.phy.0: phy poweron failed --> -110
>
> And the (non-PHY_)AUX_CLK is necessary for at least one of them, as
> removing it causes a crash on boot
>
> Konrad
Hi Konrad, Johan
I tried remove PHY_AUX_CLK in sa8775p platform like this, and
it will cause a crash on boot. And I checked the clock documentation
for sa8775p and found that the PHY_AUX_CLK is also required.
The changes are as follows:
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -7887,7 +7887,7 @@ pcie1_phy: phy@1c14000 {
compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy";
reg = <0x0 0x1c14000 0x0 0x4000>;
- clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
+ clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
<&gcc GCC_PCIE_CLKREF_EN>,
<&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
BRs
Ziyue
On Tue, Jul 22, 2025 at 01:13:34PM +0800, Ziyue Zhang wrote:
> On 7/18/2025 6:53 PM, Konrad Dybcio wrote:
> > On 7/18/25 12:02 PM, Johan Hovold wrote:
> >> On Fri, Jul 18, 2025 at 04:17:17PM +0800, Ziyue Zhang wrote:
> >>> gcc_aux_clk is used in PCIe RC and it is not required in pcie phy, in
> >>> pcie phy it should be gcc_phy_aux_clk, so remove gcc_aux_clk and
> >>> replace it with gcc_phy_aux_clk.
> >> Expanding on why this is a correct change would be good since this does
> >> not yet seem to have been fully resolved:
> >>
> >> https://lore.kernel.org/lkml/98088092-1987-41cc-ab70-c9a5d3fdbb41@oss.qualcomm.com/
> > I dug out some deep memories and recalled that _PHY_AUX_CLK was
> > necessary on x1e for the Gen4 PHY to initialize properly. This
> > can be easily reproduced:
> > @@ -3312,7 +3312,7 @@ pcie3_phy: phy@1be0000 {
> > compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy";
> > reg = <0 0x01be0000 0 0x10000>;
> >
> > - clocks = <&gcc GCC_PCIE_3_PHY_AUX_CLK>,
> > + clocks = <&gcc GCC_PCIE_3_AUX_CLK>,
> > <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
> > <&tcsr TCSR_PCIE_8L_CLKREF_EN>,
> > <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>,
> >
> > ==>
> > [ 6.967231] qcom-qmp-pcie-phy 1be0000.phy: phy initialization timed-out
> > [ 6.974462] phy phy-1be0000.phy.0: phy poweron failed --> -110
> >
> > And the (non-PHY_)AUX_CLK is necessary for at least one of them, as
> > removing it causes a crash on boot
Thanks for checking. I too had noticed that the pcie4 and pcie5 was
using the non-phy aux clocks, and those are indeed gen3.
> I tried remove PHY_AUX_CLK in sa8775p platform like this, and
> it will cause a crash on boot. And I checked the clock documentation
> for sa8775p and found that the PHY_AUX_CLK is also required.
Thanks, would still be good to say something in the commit message about
the difference between the PHY_AUX_CLK and AUX_CLK clocks and why
(only?) the gen4 PHYs need it (we seem to have other Qualcomm non-gen4
PHYs using the PHY_AUX clock too).
That is, please clarify which PHYs need the PHY_AUX_CLK and why they
don't also need the AUX_CLK like some PHYs do.
Johan
On 7/18/2025 6:53 PM, Konrad Dybcio wrote:
> On 7/18/25 12:02 PM, Johan Hovold wrote:
>> On Fri, Jul 18, 2025 at 04:17:17PM +0800, Ziyue Zhang wrote:
>>> gcc_aux_clk is used in PCIe RC and it is not required in pcie phy, in
>>> pcie phy it should be gcc_phy_aux_clk, so remove gcc_aux_clk and
>>> replace it with gcc_phy_aux_clk.
>> Expanding on why this is a correct change would be good since this does
>> not yet seem to have been fully resolved:
>>
>> https://lore.kernel.org/lkml/98088092-1987-41cc-ab70-c9a5d3fdbb41@oss.qualcomm.com/
> I dug out some deep memories and recalled that _PHY_AUX_CLK was
> necessary on x1e for the Gen4 PHY to initialize properly. This
> can be easily reproduced:
>
> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> index a9a7bb676c6f..d5ef6bef2b23 100644
> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> @@ -3312,7 +3312,7 @@ pcie3_phy: phy@1be0000 {
> compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy";
> reg = <0 0x01be0000 0 0x10000>;
>
> - clocks = <&gcc GCC_PCIE_3_PHY_AUX_CLK>,
> + clocks = <&gcc GCC_PCIE_3_AUX_CLK>,
> <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
> <&tcsr TCSR_PCIE_8L_CLKREF_EN>,
> <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>,
>
> ==>
> [ 6.967231] qcom-qmp-pcie-phy 1be0000.phy: phy initialization timed-out
> [ 6.974462] phy phy-1be0000.phy.0: phy poweron failed --> -110
>
> And the (non-PHY_)AUX_CLK is necessary for at least one of them, as
> removing it causes a crash on boot
>
> Konrad
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