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charset="utf-8" gcc_aux_clk is used in PCIe RC and it is not required in pcie phy, in pcie phy it should be gcc_phy_aux_clk, so remove gcc_aux_clk and replace it with gcc_phy_aux_clk. Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 28 +++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qc= om/sa8775p.dtsi index 9997a29901f5..39a4f59d8925 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -7707,16 +7707,18 @@ pcie0_phy: phy@1c04000 { compatible =3D "qcom,sa8775p-qmp-gen4x2-pcie-phy"; reg =3D <0x0 0x1c04000 0x0 0x2000>; =20 - clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>, + clocks =3D <&gcc GCC_PCIE_0_PHY_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, <&gcc GCC_PCIE_CLKREF_EN>, <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_0_PIPE_CLK>, - <&gcc GCC_PCIE_0_PIPEDIV2_CLK>, - <&gcc GCC_PCIE_0_PHY_AUX_CLK>; - - clock-names =3D "aux", "cfg_ahb", "ref", "rchng", "pipe", - "pipediv2", "phy_aux"; + <&gcc GCC_PCIE_0_PIPEDIV2_CLK>; + clock-names =3D "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; =20 assigned-clocks =3D <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; assigned-clock-rates =3D <100000000>; @@ -7873,16 +7875,18 @@ pcie1_phy: phy@1c14000 { compatible =3D "qcom,sa8775p-qmp-gen4x4-pcie-phy"; reg =3D <0x0 0x1c14000 0x0 0x4000>; =20 - clocks =3D <&gcc GCC_PCIE_1_AUX_CLK>, + clocks =3D <&gcc GCC_PCIE_1_PHY_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, <&gcc GCC_PCIE_CLKREF_EN>, <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_1_PIPE_CLK>, - <&gcc GCC_PCIE_1_PIPEDIV2_CLK>, - <&gcc GCC_PCIE_1_PHY_AUX_CLK>; - - clock-names =3D "aux", "cfg_ahb", "ref", "rchng", "pipe", - "pipediv2", "phy_aux"; + <&gcc GCC_PCIE_1_PIPEDIV2_CLK>; + clock-names =3D "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; =20 assigned-clocks =3D <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; assigned-clock-rates =3D <100000000>; --=20 2.34.1