From: Abhinav Kumar <quic_abhinavk@quicinc.com>
On some chipsets such as qcom,sa8775p-dp, qcom,sm8650-dp and some more,
the display port controller can support more than one pixel stream
(multi-stream transport).
These chipsets can support up to 4 stream pixel clocks for display port
controller. To support MST on these platforms, add the appropriate
stream pixel clock bindings
Since this mode is not supported on all chipsets, add exception
rules and min/max items to clearly mark which chipsets support
only SST mode (single stream) and which ones support MST.
Note: On chipsets that do support MST, the number of streams supported
can vary between controllers. For example, SA8775P supports 4 MST
streams on mdss_dp0 but only 2 streams on mdss_dp1.
In addition, many chipsets depend on the "sm8350-dp" compatibility
string but not all (ex. SM6350) support MST. Because of these reasons,
the min/maxItem for MST-supported platforms is a range of 5-8.
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com>
---
.../bindings/display/msm/dp-controller.yaml | 36 +++++++++++++++++++++-
.../bindings/display/msm/qcom,sa8775p-mdss.yaml | 10 ++++--
.../bindings/display/msm/qcom,sar2130p-mdss.yaml | 6 ++--
.../bindings/display/msm/qcom,sc7280-mdss.yaml | 6 ++--
.../bindings/display/msm/qcom,sm8750-mdss.yaml | 6 ++--
.../bindings/display/msm/qcom,x1e80100-mdss.yaml | 6 ++--
6 files changed, 59 insertions(+), 11 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
index d8d94f62c102..2893f097df82 100644
--- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
@@ -58,20 +58,28 @@ properties:
maxItems: 1
clocks:
+ minItems: 5
items:
- description: AHB clock to enable register access
- description: Display Port AUX clock
- description: Display Port Link clock
- description: Link interface clock between DP and PHY
- - description: Display Port Pixel clock
+ - description: Display Port stream 0 Pixel clock
+ - description: Display Port stream 1 Pixel clock
+ - description: Display Port stream 2 Pixel clock
+ - description: Display Port stream 3 Pixel clock
clock-names:
+ minItems: 5
items:
- const: core_iface
- const: core_aux
- const: ctrl_link
- const: ctrl_link_iface
- const: stream_pixel
+ - const: stream_1_pixel
+ - const: stream_2_pixel
+ - const: stream_3_pixel
phys:
maxItems: 1
@@ -173,6 +181,32 @@ allOf:
required:
- "#sound-dai-cells"
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sa8775p-dp
+ - qcom,sc7280-dp
+ - qcom,sc8180x-dp
+ - qcom,sc8280xp-dp
+ - qcom,sc8280xp-edp
+ - qcom,sm8150-dp
+ - qcom,sm8350-dp
+ - qcom,sm8650-dp
+ - qcom,x1e80100-dp
+ then:
+ properties:
+ clocks:
+ minItems: 5
+ maxItems: 8
+
+ else:
+ properties:
+ clocks:
+ minItems: 5
+ maxItems: 5
+
additionalProperties: false
examples:
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
index 2dc76a074da1..0af1e5cd1691 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
@@ -384,12 +384,18 @@ examples:
<&dispcc_dptx0_aux_clk>,
<&dispcc_dptx0_link_clk>,
<&dispcc_dptx0_link_intf_clk>,
- <&dispcc_dptx0_pixel0_clk>;
+ <&dispcc_dptx0_pixel0_clk>,
+ <&dispcc_dptx0_pixel1_clk>,
+ <&dispcc_dptx0_pixel2_clk>,
+ <&dispcc_dptx0_pixel3_clk>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel",
+ "stream_2_pixel",
+ "stream_3_pixel";
phys = <&mdss0_dp0_phy>;
phy-names = "dp";
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml
index eef5627133db..0a8bda583469 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml
@@ -207,12 +207,14 @@ examples:
<&dispcc_disp_cc_mdss_dptx0_aux_clk>,
<&dispcc_disp_cc_mdss_dptx0_link_clk>,
<&dispcc_disp_cc_mdss_dptx0_link_intf_clk>,
- <&dispcc_disp_cc_mdss_dptx0_pixel0_clk>;
+ <&dispcc_disp_cc_mdss_dptx0_pixel0_clk>,
+ <&dispcc_disp_cc_mdss_dptx0_pixel1_clk>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
phy-names = "dp";
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml
index 9e52ac9c0eb4..f8fffc168a71 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml
@@ -378,12 +378,14 @@ examples:
<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
phys = <&dp_phy>;
phy-names = "dp";
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml
index 0858dd61fb0f..0bc0edc41341 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml
@@ -401,12 +401,14 @@ examples:
<&disp_cc_mdss_dptx0_aux_clk>,
<&disp_cc_mdss_dptx0_link_clk>,
<&disp_cc_mdss_dptx0_link_intf_clk>,
- <&disp_cc_mdss_dptx0_pixel0_clk>;
+ <&disp_cc_mdss_dptx0_pixel0_clk>,
+ <&disp_cc_mdss_dptx0_pixel1_clk>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
operating-points-v2 = <&dp_opp_table>;
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml
index 0e699de684c8..ceb3a0b70799 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml
@@ -183,11 +183,13 @@ examples:
<&dispcc_dptx0_aux_clk>,
<&dispcc_dptx0_link_clk>,
<&dispcc_dptx0_link_intf_clk>,
- <&dispcc_dptx0_pixel0_clk>;
+ <&dispcc_dptx0_pixel0_clk>,
+ <&dispcc_dptx0_pixel1_clk>;
clock-names = "core_iface", "core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
operating-points-v2 = <&mdss_dp0_opp_table>;
--
2.50.1On Thu, Jul 17, 2025 at 04:28:46PM -0700, Jessica Zhang wrote: > From: Abhinav Kumar <quic_abhinavk@quicinc.com> > > On some chipsets such as qcom,sa8775p-dp, qcom,sm8650-dp and some more, > the display port controller can support more than one pixel stream > (multi-stream transport). > > These chipsets can support up to 4 stream pixel clocks for display port > controller. To support MST on these platforms, add the appropriate > stream pixel clock bindings > > Since this mode is not supported on all chipsets, add exception > rules and min/max items to clearly mark which chipsets support > only SST mode (single stream) and which ones support MST. > > Note: On chipsets that do support MST, the number of streams supported > can vary between controllers. For example, SA8775P supports 4 MST > streams on mdss_dp0 but only 2 streams on mdss_dp1. > > In addition, many chipsets depend on the "sm8350-dp" compatibility > string but not all (ex. SM6350) support MST. Because of these reasons, > the min/maxItem for MST-supported platforms is a range of 5-8. > > Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> > Signed-off-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com> > --- > .../bindings/display/msm/dp-controller.yaml | 36 +++++++++++++++++++++- > .../bindings/display/msm/qcom,sa8775p-mdss.yaml | 10 ++++-- > .../bindings/display/msm/qcom,sar2130p-mdss.yaml | 6 ++-- > .../bindings/display/msm/qcom,sc7280-mdss.yaml | 6 ++-- > .../bindings/display/msm/qcom,sm8750-mdss.yaml | 6 ++-- > .../bindings/display/msm/qcom,x1e80100-mdss.yaml | 6 ++-- > 6 files changed, 59 insertions(+), 11 deletions(-) I've cross-checked. We need to stop declaring SM6350 as compatible with SM8350, it doesn't provide MST support (and so there will be a need for a driver update too). Other than that, please document DP MST on SDM845. With those changes in place, I think, all platforms will be covered. -- With best wishes Dmitry
On Thu, Jul 17, 2025 at 04:28:46PM -0700, Jessica Zhang wrote: > From: Abhinav Kumar <quic_abhinavk@quicinc.com> > > On some chipsets such as qcom,sa8775p-dp, qcom,sm8650-dp and some more, > the display port controller can support more than one pixel stream > (multi-stream transport). > > These chipsets can support up to 4 stream pixel clocks for display port > controller. To support MST on these platforms, add the appropriate > stream pixel clock bindings > > Since this mode is not supported on all chipsets, add exception > rules and min/max items to clearly mark which chipsets support > only SST mode (single stream) and which ones support MST. > > Note: On chipsets that do support MST, the number of streams supported > can vary between controllers. For example, SA8775P supports 4 MST > streams on mdss_dp0 but only 2 streams on mdss_dp1. Then for this platform it should be oneOf: minItems: 6 / minItems: 8 > > In addition, many chipsets depend on the "sm8350-dp" compatibility > string but not all (ex. SM6350) support MST. Because of these reasons, > the min/maxItem for MST-supported platforms is a range of 5-8. Do we still consider them to be compatible? > > Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> > Signed-off-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com> > --- > .../bindings/display/msm/dp-controller.yaml | 36 +++++++++++++++++++++- > .../bindings/display/msm/qcom,sa8775p-mdss.yaml | 10 ++++-- > .../bindings/display/msm/qcom,sar2130p-mdss.yaml | 6 ++-- > .../bindings/display/msm/qcom,sc7280-mdss.yaml | 6 ++-- > .../bindings/display/msm/qcom,sm8750-mdss.yaml | 6 ++-- > .../bindings/display/msm/qcom,x1e80100-mdss.yaml | 6 ++-- > 6 files changed, 59 insertions(+), 11 deletions(-) > -- With best wishes Dmitry
On Thu, Jul 17, 2025 at 04:28:46PM -0700, Jessica Zhang wrote: > From: Abhinav Kumar <quic_abhinavk@quicinc.com> > > On some chipsets such as qcom,sa8775p-dp, qcom,sm8650-dp and some more, > the display port controller can support more than one pixel stream > (multi-stream transport). > > These chipsets can support up to 4 stream pixel clocks for display port > controller. To support MST on these platforms, add the appropriate > stream pixel clock bindings > > Since this mode is not supported on all chipsets, add exception > rules and min/max items to clearly mark which chipsets support > only SST mode (single stream) and which ones support MST. > > Note: On chipsets that do support MST, the number of streams supported > can vary between controllers. For example, SA8775P supports 4 MST > streams on mdss_dp0 but only 2 streams on mdss_dp1. > > In addition, many chipsets depend on the "sm8350-dp" compatibility > string but not all (ex. SM6350) support MST. Because of these reasons, > the min/maxItem for MST-supported platforms is a range of 5-8. > > Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> > Signed-off-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com> > --- > .../bindings/display/msm/dp-controller.yaml | 36 +++++++++++++++++++++- > .../bindings/display/msm/qcom,sa8775p-mdss.yaml | 10 ++++-- > .../bindings/display/msm/qcom,sar2130p-mdss.yaml | 6 ++-- > .../bindings/display/msm/qcom,sc7280-mdss.yaml | 6 ++-- > .../bindings/display/msm/qcom,sm8750-mdss.yaml | 6 ++-- > .../bindings/display/msm/qcom,x1e80100-mdss.yaml | 6 ++-- > 6 files changed, 59 insertions(+), 11 deletions(-) > > diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml > index d8d94f62c102..2893f097df82 100644 > --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml > +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml > @@ -58,20 +58,28 @@ properties: > maxItems: 1 > > clocks: > + minItems: 5 > items: > - description: AHB clock to enable register access > - description: Display Port AUX clock > - description: Display Port Link clock > - description: Link interface clock between DP and PHY > - - description: Display Port Pixel clock > + - description: Display Port stream 0 Pixel clock > + - description: Display Port stream 1 Pixel clock > + - description: Display Port stream 2 Pixel clock > + - description: Display Port stream 3 Pixel clock > > clock-names: > + minItems: 5 > items: > - const: core_iface > - const: core_aux > - const: ctrl_link > - const: ctrl_link_iface > - const: stream_pixel > + - const: stream_1_pixel > + - const: stream_2_pixel > + - const: stream_3_pixel > > phys: > maxItems: 1 > @@ -173,6 +181,32 @@ allOf: > required: > - "#sound-dai-cells" > > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,sa8775p-dp > + - qcom,sc7280-dp > + - qcom,sc8180x-dp > + - qcom,sc8280xp-dp > + - qcom,sc8280xp-edp > + - qcom,sm8150-dp > + - qcom,sm8350-dp > + - qcom,sm8650-dp > + - qcom,x1e80100-dp > + then: > + properties: > + clocks: > + minItems: 5 > + maxItems: 8 The hardware can't have variable list of clocks. Please describe the hardware here, specifying exact number of clocks to be used. > + > + else: > + properties: > + clocks: > + minItems: 5 > + maxItems: 5 > + > additionalProperties: false > > examples: -- With best wishes Dmitry
On Thu, Jul 17, 2025 at 04:28:46PM -0700, Jessica Zhang wrote: > From: Abhinav Kumar <quic_abhinavk@quicinc.com> > > On some chipsets such as qcom,sa8775p-dp, qcom,sm8650-dp and some more, > the display port controller can support more than one pixel stream > (multi-stream transport). > > These chipsets can support up to 4 stream pixel clocks for display port > controller. To support MST on these platforms, add the appropriate > stream pixel clock bindings > > Since this mode is not supported on all chipsets, add exception > rules and min/max items to clearly mark which chipsets support > only SST mode (single stream) and which ones support MST. > > Note: On chipsets that do support MST, the number of streams supported > can vary between controllers. For example, SA8775P supports 4 MST > streams on mdss_dp0 but only 2 streams on mdss_dp1. > > In addition, many chipsets depend on the "sm8350-dp" compatibility > string but not all (ex. SM6350) support MST. Because of these reasons, > the min/maxItem for MST-supported platforms is a range of 5-8. Then you need to rework if:. Don't use contains for the sm8350-dp, but list the front compatibles supporting. > > Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> > Signed-off-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com> > --- > .../bindings/display/msm/dp-controller.yaml | 36 +++++++++++++++++++++- > .../bindings/display/msm/qcom,sa8775p-mdss.yaml | 10 ++++-- > .../bindings/display/msm/qcom,sar2130p-mdss.yaml | 6 ++-- > .../bindings/display/msm/qcom,sc7280-mdss.yaml | 6 ++-- > .../bindings/display/msm/qcom,sm8750-mdss.yaml | 6 ++-- > .../bindings/display/msm/qcom,x1e80100-mdss.yaml | 6 ++-- > 6 files changed, 59 insertions(+), 11 deletions(-) > > diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml > index d8d94f62c102..2893f097df82 100644 > --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml > +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml > @@ -58,20 +58,28 @@ properties: > maxItems: 1 > > clocks: > + minItems: 5 > items: > - description: AHB clock to enable register access > - description: Display Port AUX clock > - description: Display Port Link clock > - description: Link interface clock between DP and PHY > - - description: Display Port Pixel clock > + - description: Display Port stream 0 Pixel clock > + - description: Display Port stream 1 Pixel clock > + - description: Display Port stream 2 Pixel clock > + - description: Display Port stream 3 Pixel clock > > clock-names: > + minItems: 5 > items: > - const: core_iface > - const: core_aux > - const: ctrl_link > - const: ctrl_link_iface > - const: stream_pixel > + - const: stream_1_pixel > + - const: stream_2_pixel > + - const: stream_3_pixel > > phys: > maxItems: 1 > @@ -173,6 +181,32 @@ allOf: > required: > - "#sound-dai-cells" > > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,sa8775p-dp > + - qcom,sc7280-dp > + - qcom,sc8180x-dp > + - qcom,sc8280xp-dp > + - qcom,sc8280xp-edp > + - qcom,sm8150-dp > + - qcom,sm8350-dp > + - qcom,sm8650-dp > + - qcom,x1e80100-dp > + then: > + properties: > + clocks: > + minItems: 5 > + maxItems: 8 This if is redundant, drop. > + > + else: > + properties: > + clocks: > + minItems: 5 > + maxItems: 5 Only this part has an actual effect. Best regards, Krzysztof
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