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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23e3b5e3cb7sm2002195ad.17.2025.07.17.16.28.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Jul 2025 16:28:58 -0700 (PDT) From: Jessica Zhang Date: Thu, 17 Jul 2025 16:28:46 -0700 Subject: [PATCH v3 4/5] dt-bindings: display/msm: add stream pixel clock bindings for MST Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250717-dp_mst_bindings-v3-4-72ce08285703@oss.qualcomm.com> References: <20250717-dp_mst_bindings-v3-0-72ce08285703@oss.qualcomm.com> In-Reply-To: <20250717-dp_mst_bindings-v3-0-72ce08285703@oss.qualcomm.com> To: Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Abel Vesa , Bjorn Andersson , Michael Turquette , Stephen Boyd , Mahadevan , Krishna Manikandan , Konrad Dybcio , Rob Clark , Abhinav Kumar , Jessica Zhang , Danila Tikhonov , cros-qcom-dts-watchers@chromium.org, Rob Clark Cc: Abhinav Kumar , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Krzysztof Kozlowski , Yongxing Mou X-Mailer: b4 0.15-dev-a9b2a X-Developer-Signature: v=1; a=ed25519-sha256; t=1752794927; l=9121; i=jessica.zhang@oss.qualcomm.com; s=20230329; h=from:subject:message-id; bh=lan3Y5KBTR4cC/ZtMB5SWaedJPpSyDvP8y8bQq9zCvE=; b=03eVzWqFidZ25JCpT9tqz5QUjDSx8ROwLmP2YHgRtifUoqZFZLYxbfvtojjYFYbp6auumdoDV x1KCbFJSL3pB3unjE//ooy8DahduBmsIAsAICXBdlJl0Er/9xwN22r0 X-Developer-Key: i=jessica.zhang@oss.qualcomm.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Authority-Analysis: v=2.4 cv=dKimmPZb c=1 sm=1 tr=0 ts=6879873c cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=iZctjB8Tiv542dVYzCoA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: S2BzONdcWZnI7m_v72M0BLqM-TQ2tCLU X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzE3MDIwNiBTYWx0ZWRfX0CSvmMa6VH3F /+JZ3IJFiHskb81TkppZZE+dYHf9d9Jiq/+T5hOCiD58b95f22BCt52ubEtFG6QLznVaoB3oIAh voYQmvHyKiW3yXvUKMTtv473kfTkYWOLmSQWKZ8P+qbmE5BZhZZ9x0NkIXDvlWYIVfkIWyX2WB7 wnRxB0vUz53ENVwgv7N4JSMGWxWSAVGgWAvc9YQN5aXGF6yEXQoQRrbOFrKk/mV90/pngBCuWeY hwUNOqduHXX9uJ59dAjqnNDe+AkDp4pOMSP1OzCQz3gLPCEUfNY7ABo8duejtX9w4H2ALZtcAlg i3/ig/18JxCWbka5djpeoNmPVrm53lHuxQb6bl+0fsZJdC+MS6X3QJyj2jG20GeGL5/HjooChIo TWQ5ZOeJIgtDhk8kfV6lmIXq1BT5giPPnrUcH7GIDaY1hR6cyy7uqEBj9U6RLT4c1uWwvgP6 X-Proofpoint-ORIG-GUID: S2BzONdcWZnI7m_v72M0BLqM-TQ2tCLU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-17_04,2025-07-17_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 mlxlogscore=999 mlxscore=0 spamscore=0 adultscore=0 impostorscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 phishscore=0 lowpriorityscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507170206 From: Abhinav Kumar On some chipsets such as qcom,sa8775p-dp, qcom,sm8650-dp and some more, the display port controller can support more than one pixel stream (multi-stream transport). These chipsets can support up to 4 stream pixel clocks for display port controller. To support MST on these platforms, add the appropriate stream pixel clock bindings Since this mode is not supported on all chipsets, add exception rules and min/max items to clearly mark which chipsets support only SST mode (single stream) and which ones support MST. Note: On chipsets that do support MST, the number of streams supported can vary between controllers. For example, SA8775P supports 4 MST streams on mdss_dp0 but only 2 streams on mdss_dp1. In addition, many chipsets depend on the "sm8350-dp" compatibility string but not all (ex. SM6350) support MST. Because of these reasons, the min/maxItem for MST-supported platforms is a range of 5-8. Signed-off-by: Abhinav Kumar Signed-off-by: Jessica Zhang --- .../bindings/display/msm/dp-controller.yaml | 36 ++++++++++++++++++= +++- .../bindings/display/msm/qcom,sa8775p-mdss.yaml | 10 ++++-- .../bindings/display/msm/qcom,sar2130p-mdss.yaml | 6 ++-- .../bindings/display/msm/qcom,sc7280-mdss.yaml | 6 ++-- .../bindings/display/msm/qcom,sm8750-mdss.yaml | 6 ++-- .../bindings/display/msm/qcom,x1e80100-mdss.yaml | 6 ++-- 6 files changed, 59 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.ya= ml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index d8d94f62c102..2893f097df82 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -58,20 +58,28 @@ properties: maxItems: 1 =20 clocks: + minItems: 5 items: - description: AHB clock to enable register access - description: Display Port AUX clock - description: Display Port Link clock - description: Link interface clock between DP and PHY - - description: Display Port Pixel clock + - description: Display Port stream 0 Pixel clock + - description: Display Port stream 1 Pixel clock + - description: Display Port stream 2 Pixel clock + - description: Display Port stream 3 Pixel clock =20 clock-names: + minItems: 5 items: - const: core_iface - const: core_aux - const: ctrl_link - const: ctrl_link_iface - const: stream_pixel + - const: stream_1_pixel + - const: stream_2_pixel + - const: stream_3_pixel =20 phys: maxItems: 1 @@ -173,6 +181,32 @@ allOf: required: - "#sound-dai-cells" =20 + - if: + properties: + compatible: + contains: + enum: + - qcom,sa8775p-dp + - qcom,sc7280-dp + - qcom,sc8180x-dp + - qcom,sc8280xp-dp + - qcom,sc8280xp-edp + - qcom,sm8150-dp + - qcom,sm8350-dp + - qcom,sm8650-dp + - qcom,x1e80100-dp + then: + properties: + clocks: + minItems: 5 + maxItems: 8 + + else: + properties: + clocks: + minItems: 5 + maxItems: 5 + additionalProperties: false =20 examples: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mds= s.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.ya= ml index 2dc76a074da1..0af1e5cd1691 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml @@ -384,12 +384,18 @@ examples: <&dispcc_dptx0_aux_clk>, <&dispcc_dptx0_link_clk>, <&dispcc_dptx0_link_intf_clk>, - <&dispcc_dptx0_pixel0_clk>; + <&dispcc_dptx0_pixel0_clk>, + <&dispcc_dptx0_pixel1_clk>, + <&dispcc_dptx0_pixel2_clk>, + <&dispcc_dptx0_pixel3_clk>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel", + "stream_2_pixel", + "stream_3_pixel"; =20 phys =3D <&mdss0_dp0_phy>; phy-names =3D "dp"; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-md= ss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.= yaml index eef5627133db..0a8bda583469 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml @@ -207,12 +207,14 @@ examples: <&dispcc_disp_cc_mdss_dptx0_aux_clk>, <&dispcc_disp_cc_mdss_dptx0_link_clk>, <&dispcc_disp_cc_mdss_dptx0_link_intf_clk>, - <&dispcc_disp_cc_mdss_dptx0_pixel0_clk>; + <&dispcc_disp_cc_mdss_dptx0_pixel0_clk>, + <&dispcc_disp_cc_mdss_dptx0_pixel1_clk>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; =20 phys =3D <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; phy-names =3D "dp"; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss= .yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml index 9e52ac9c0eb4..f8fffc168a71 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml @@ -378,12 +378,14 @@ examples: <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; phys =3D <&dp_phy>; phy-names =3D "dp"; =20 diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss= .yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml index 0858dd61fb0f..0bc0edc41341 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml @@ -401,12 +401,14 @@ examples: <&disp_cc_mdss_dptx0_aux_clk>, <&disp_cc_mdss_dptx0_link_clk>, <&disp_cc_mdss_dptx0_link_intf_clk>, - <&disp_cc_mdss_dptx0_pixel0_clk>; + <&disp_cc_mdss_dptx0_pixel0_clk>, + <&disp_cc_mdss_dptx0_pixel1_clk>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; =20 operating-points-v2 =3D <&dp_opp_table>; =20 diff --git a/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-md= ss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.= yaml index 0e699de684c8..ceb3a0b70799 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml @@ -183,11 +183,13 @@ examples: <&dispcc_dptx0_aux_clk>, <&dispcc_dptx0_link_clk>, <&dispcc_dptx0_link_intf_clk>, - <&dispcc_dptx0_pixel0_clk>; + <&dispcc_dptx0_pixel0_clk>, + <&dispcc_dptx0_pixel1_clk>; clock-names =3D "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; =20 operating-points-v2 =3D <&mdss_dp0_opp_table>; =20 --=20 2.50.1