arm64: dts: qcom: ipq5424: add i2c nodes

[PATCH v1] arm64: dts: qcom: ipq5424: add i2c nodes

Posted by Manikanta Mylavarapu 2 months, 3 weeks ago

Serial engines 2 and 3 on the IPQ5424 support I2C. The I2C instance
operates on serial engine 2, designated as i2c0, and on serial engine 3,
designated as i2c1. Add both the i2c0 and i2c1 nodes.

Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
---
 arch/arm64/boot/dts/qcom/ipq5424.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
index 66bd2261eb25..858b9c714a13 100644
--- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
@@ -425,6 +425,28 @@ uart1: serial@1a84000 {
 				interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
+			i2c0: i2c@1a88000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x01a88000 0 0x4000>;
+				clocks = <&gcc GCC_QUPV3_I2C0_CLK>;
+				clock-names = "se";
+				interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
+				assigned-clocks = <&gcc GCC_QUPV3_I2C0_CLK>;
+				assigned-clock-rates = <64000000>;
+				status = "disabled";
+			};
+
+			i2c1: i2c@1a8c000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x01a8c000 0 0x4000>;
+				clocks = <&gcc GCC_QUPV3_I2C1_CLK>;
+				clock-names = "se";
+				interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
+				assigned-clocks = <&gcc GCC_QUPV3_I2C1_CLK>;
+				assigned-clock-rates = <64000000>;
+				status = "disabled";
+			};
+
 			spi0: spi@1a90000 {
 				compatible = "qcom,geni-spi";
 				reg = <0 0x01a90000 0 0x4000>;

base-commit: 58ba80c4740212c29a1cf9b48f588e60a7612209
-- 
2.34.1

Re: [PATCH v1] arm64: dts: qcom: ipq5424: add i2c nodes

Posted by Konrad Dybcio 2 months, 1 week ago

On 7/11/25 1:14 PM, Manikanta Mylavarapu wrote:
> Serial engines 2 and 3 on the IPQ5424 support I2C. The I2C instance
> operates on serial engine 2, designated as i2c0, and on serial engine 3,
> designated as i2c1. Add both the i2c0 and i2c1 nodes.
> 
> Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/ipq5424.dtsi | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
> index 66bd2261eb25..858b9c714a13 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
> @@ -425,6 +425,28 @@ uart1: serial@1a84000 {
>  				interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
>  			};
>  
> +			i2c0: i2c@1a88000 {
> +				compatible = "qcom,geni-i2c";
> +				reg = <0 0x01a88000 0 0x4000>;
> +				clocks = <&gcc GCC_QUPV3_I2C0_CLK>;
> +				clock-names = "se";
> +				interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
> +				assigned-clocks = <&gcc GCC_QUPV3_I2C0_CLK>;
> +				assigned-clock-rates = <64000000>;

This is very wrong, the in-driver handling should be enough.
If not, add an opp-table.

Konrad

Re: [PATCH v1] arm64: dts: qcom: ipq5424: add i2c nodes

Posted by Manikanta Mylavarapu 1 month, 3 weeks ago


On 7/30/2025 5:13 PM, Konrad Dybcio wrote:
> On 7/11/25 1:14 PM, Manikanta Mylavarapu wrote:
>> Serial engines 2 and 3 on the IPQ5424 support I2C. The I2C instance
>> operates on serial engine 2, designated as i2c0, and on serial engine 3,
>> designated as i2c1. Add both the i2c0 and i2c1 nodes.
>>
>> Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
>> ---
>>  arch/arm64/boot/dts/qcom/ipq5424.dtsi | 22 ++++++++++++++++++++++
>>  1 file changed, 22 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>> index 66bd2261eb25..858b9c714a13 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>> @@ -425,6 +425,28 @@ uart1: serial@1a84000 {
>>  				interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
>>  			};
>>  
>> +			i2c0: i2c@1a88000 {
>> +				compatible = "qcom,geni-i2c";
>> +				reg = <0 0x01a88000 0 0x4000>;
>> +				clocks = <&gcc GCC_QUPV3_I2C0_CLK>;
>> +				clock-names = "se";
>> +				interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
>> +				assigned-clocks = <&gcc GCC_QUPV3_I2C0_CLK>;
>> +				assigned-clock-rates = <64000000>;
> 
> This is very wrong, the in-driver handling should be enough.
> If not, add an opp-table.
> 

Hi Konrad,

Thank you for your review and valuable feedback.
I will incorporate an opp-table entry with a 64MHz frequency and submit a revised patch.

Thanks & Regards,
Manikanta.