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[PATCH v2 2/7] pinctrl: renesas: rzg2l: parameterize OEN register offset

Prabhakar posted 7 patches 7 months ago
There is a newer version of this series
[PATCH v2 2/7] pinctrl: renesas: rzg2l: parameterize OEN register offset
Posted by Prabhakar 7 months ago 
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Prepare for supporting SoCs with varying OEN register locations by
parameterizing the OEN offset in the rzg2l driver. Introduce an `oen`
field in the rzg2l_register_offsets structure and update rzg2l_read_oen(),
rzg2l_write_oen(), suspend/resume caching, and SoC hwcfg entries to use
this offset instead of the hard-coded ETH_MODE value.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/pinctrl/renesas/pinctrl-rzg2l.c | 23 ++++++++++++++---------
 1 file changed, 14 insertions(+), 9 deletions(-)

diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index af4a40ca0a98..75b5bd032659 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -146,7 +146,6 @@
 #define SD_CH(off, ch)		((off) + (ch) * 4)
 #define ETH_POC(off, ch)	((off) + (ch) * 4)
 #define QSPI			(0x3008)
-#define ETH_MODE		(0x3018)
 #define PFC_OEN			(0x3C40) /* known on RZ/V2H(P) only */
 
 #define PVDD_2500		2	/* I/O domain voltage 2.5V */
@@ -221,11 +220,13 @@ static const struct pin_config_item renesas_rzv2h_conf_items[] = {
  * @pwpr: PWPR register offset
  * @sd_ch: SD_CH register offset
  * @eth_poc: ETH_POC register offset
+ * @oen: OEN register offset
  */
 struct rzg2l_register_offsets {
 	u16 pwpr;
 	u16 sd_ch;
 	u16 eth_poc;
+	u16 oen;
 };
 
 /**
@@ -1073,11 +1074,12 @@ static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
 	if (bit < 0)
 		return 0;
 
-	return !(readb(pctrl->base + ETH_MODE) & BIT(bit));
+	return !(readb(pctrl->base + pctrl->data->hwcfg->regs.oen) & BIT(bit));
 }
 
 static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)
 {
+	u16 oen_offset = pctrl->data->hwcfg->regs.oen;
 	unsigned long flags;
 	int bit;
 	u8 val;
@@ -1087,12 +1089,12 @@ static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oe
 		return bit;
 
 	spin_lock_irqsave(&pctrl->lock, flags);
-	val = readb(pctrl->base + ETH_MODE);
+	val = readb(pctrl->base + oen_offset);
 	if (oen)
 		val &= ~BIT(bit);
 	else
 		val |= BIT(bit);
-	writeb(val, pctrl->base + ETH_MODE);
+	writeb(val, pctrl->base + oen_offset);
 	spin_unlock_irqrestore(&pctrl->lock, flags);
 
 	return 0;
@@ -1126,11 +1128,12 @@ static u32 rzg3s_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
 	if (bit < 0)
 		return 0;
 
-	return !(readb(pctrl->base + ETH_MODE) & BIT(bit));
+	return !(readb(pctrl->base + pctrl->data->hwcfg->regs.oen) & BIT(bit));
 }
 
 static int rzg3s_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)
 {
+	u16 oen_offset = pctrl->data->hwcfg->regs.oen;
 	unsigned long flags;
 	int bit;
 	u8 val;
@@ -1140,12 +1143,12 @@ static int rzg3s_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oe
 		return bit;
 
 	spin_lock_irqsave(&pctrl->lock, flags);
-	val = readb(pctrl->base + ETH_MODE);
+	val = readb(pctrl->base + oen_offset);
 	if (oen)
 		val &= ~BIT(bit);
 	else
 		val |= BIT(bit);
-	writeb(val, pctrl->base + ETH_MODE);
+	writeb(val, pctrl->base + oen_offset);
 	spin_unlock_irqrestore(&pctrl->lock, flags);
 
 	return 0;
@@ -3164,7 +3167,7 @@ static int rzg2l_pinctrl_suspend_noirq(struct device *dev)
 	}
 
 	cache->qspi = readb(pctrl->base + QSPI);
-	cache->eth_mode = readb(pctrl->base + ETH_MODE);
+	cache->eth_mode = readb(pctrl->base + pctrl->data->hwcfg->regs.oen);
 
 	if (!atomic_read(&pctrl->wakeup_path))
 		clk_disable_unprepare(pctrl->clk);
@@ -3189,7 +3192,7 @@ static int rzg2l_pinctrl_resume_noirq(struct device *dev)
 	}
 
 	writeb(cache->qspi, pctrl->base + QSPI);
-	writeb(cache->eth_mode, pctrl->base + ETH_MODE);
+	writeb(cache->eth_mode, pctrl->base + pctrl->data->hwcfg->regs.oen);
 	for (u8 i = 0; i < 2; i++) {
 		if (regs->sd_ch)
 			writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i));
@@ -3241,6 +3244,7 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg = {
 		.pwpr = 0x3014,
 		.sd_ch = 0x3000,
 		.eth_poc = 0x300c,
+		.oen = 0x3018,
 	},
 	.iolh_groupa_ua = {
 		/* 3v3 power source */
@@ -3256,6 +3260,7 @@ static const struct rzg2l_hwcfg rzg3s_hwcfg = {
 		.pwpr = 0x3000,
 		.sd_ch = 0x3004,
 		.eth_poc = 0x3010,
+		.oen = 0x3018,
 	},
 	.iolh_groupa_ua = {
 		/* 1v8 power source */
-- 
2.49.0
Re: [PATCH v2 2/7] pinctrl: renesas: rzg2l: parameterize OEN register offset
Posted by Geert Uytterhoeven 6 months, 1 week ago 
Hi Prabhakar,

On Wed, 9 Jul 2025 at 18:08, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Prepare for supporting SoCs with varying OEN register locations by
> parameterizing the OEN offset in the rzg2l driver. Introduce an `oen`
> field in the rzg2l_register_offsets structure and update rzg2l_read_oen(),
> rzg2l_write_oen(), suspend/resume caching, and SoC hwcfg entries to use
> this offset instead of the hard-coded ETH_MODE value.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c

> @@ -3164,7 +3167,7 @@ static int rzg2l_pinctrl_suspend_noirq(struct device *dev)
>         }
>
>         cache->qspi = readb(pctrl->base + QSPI);
> -       cache->eth_mode = readb(pctrl->base + ETH_MODE);
> +       cache->eth_mode = readb(pctrl->base + pctrl->data->hwcfg->regs.oen);

You still have the eth_mode name in the rzg2l_pinctrl_reg_cache
structure; probably you want to rename that as well.
In addition, it is saved/restored unconditionally, even if regs.oen
is zero, which is the case for RZ/V2H, RZ/V2N, and RZ/G3E until
[PATCH v2 5/7].

The rest LGTM.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
Re: [PATCH v2 2/7] pinctrl: renesas: rzg2l: parameterize OEN register offset
Posted by Lad, Prabhakar 6 months, 1 week ago 
Hi Geert,

Thank you for the review.

On Wed, Aug 6, 2025 at 1:53 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Wed, 9 Jul 2025 at 18:08, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Prepare for supporting SoCs with varying OEN register locations by
> > parameterizing the OEN offset in the rzg2l driver. Introduce an `oen`
> > field in the rzg2l_register_offsets structure and update rzg2l_read_oen(),
> > rzg2l_write_oen(), suspend/resume caching, and SoC hwcfg entries to use
> > this offset instead of the hard-coded ETH_MODE value.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
>
> > @@ -3164,7 +3167,7 @@ static int rzg2l_pinctrl_suspend_noirq(struct device *dev)
> >         }
> >
> >         cache->qspi = readb(pctrl->base + QSPI);
> > -       cache->eth_mode = readb(pctrl->base + ETH_MODE);
> > +       cache->eth_mode = readb(pctrl->base + pctrl->data->hwcfg->regs.oen);
>
> You still have the eth_mode name in the rzg2l_pinctrl_reg_cache
> structure; probably you want to rename that as well.
Agreed, I will rename it to oen.

> In addition, it is saved/restored unconditionally, even if regs.oen
> is zero, which is the case for RZ/V2H, RZ/V2N, and RZ/G3E until
> [PATCH v2 5/7].
>
Ahh right, I will add a check in this patch and later drop it in 5/7.

Cheers,
Prabhakar

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