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Wed, 09 Jul 2025 09:08:33 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , John Madieu , Lad Prabhakar Subject: [PATCH v2 2/7] pinctrl: renesas: rzg2l: parameterize OEN register offset Date: Wed, 9 Jul 2025 17:08:14 +0100 Message-ID: <20250709160819.306875-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250709160819.306875-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250709160819.306875-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Prepare for supporting SoCs with varying OEN register locations by parameterizing the OEN offset in the rzg2l driver. Introduce an `oen` field in the rzg2l_register_offsets structure and update rzg2l_read_oen(), rzg2l_write_oen(), suspend/resume caching, and SoC hwcfg entries to use this offset instead of the hard-coded ETH_MODE value. Signed-off-by: Lad Prabhakar --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index af4a40ca0a98..75b5bd032659 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -146,7 +146,6 @@ #define SD_CH(off, ch) ((off) + (ch) * 4) #define ETH_POC(off, ch) ((off) + (ch) * 4) #define QSPI (0x3008) -#define ETH_MODE (0x3018) #define PFC_OEN (0x3C40) /* known on RZ/V2H(P) only */ =20 #define PVDD_2500 2 /* I/O domain voltage 2.5V */ @@ -221,11 +220,13 @@ static const struct pin_config_item renesas_rzv2h_con= f_items[] =3D { * @pwpr: PWPR register offset * @sd_ch: SD_CH register offset * @eth_poc: ETH_POC register offset + * @oen: OEN register offset */ struct rzg2l_register_offsets { u16 pwpr; u16 sd_ch; u16 eth_poc; + u16 oen; }; =20 /** @@ -1073,11 +1074,12 @@ static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pct= rl, unsigned int _pin) if (bit < 0) return 0; =20 - return !(readb(pctrl->base + ETH_MODE) & BIT(bit)); + return !(readb(pctrl->base + pctrl->data->hwcfg->regs.oen) & BIT(bit)); } =20 static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin,= u8 oen) { + u16 oen_offset =3D pctrl->data->hwcfg->regs.oen; unsigned long flags; int bit; u8 val; @@ -1087,12 +1089,12 @@ static int rzg2l_write_oen(struct rzg2l_pinctrl *pc= trl, unsigned int _pin, u8 oe return bit; =20 spin_lock_irqsave(&pctrl->lock, flags); - val =3D readb(pctrl->base + ETH_MODE); + val =3D readb(pctrl->base + oen_offset); if (oen) val &=3D ~BIT(bit); else val |=3D BIT(bit); - writeb(val, pctrl->base + ETH_MODE); + writeb(val, pctrl->base + oen_offset); spin_unlock_irqrestore(&pctrl->lock, flags); =20 return 0; @@ -1126,11 +1128,12 @@ static u32 rzg3s_oen_read(struct rzg2l_pinctrl *pct= rl, unsigned int _pin) if (bit < 0) return 0; =20 - return !(readb(pctrl->base + ETH_MODE) & BIT(bit)); + return !(readb(pctrl->base + pctrl->data->hwcfg->regs.oen) & BIT(bit)); } =20 static int rzg3s_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin,= u8 oen) { + u16 oen_offset =3D pctrl->data->hwcfg->regs.oen; unsigned long flags; int bit; u8 val; @@ -1140,12 +1143,12 @@ static int rzg3s_oen_write(struct rzg2l_pinctrl *pc= trl, unsigned int _pin, u8 oe return bit; =20 spin_lock_irqsave(&pctrl->lock, flags); - val =3D readb(pctrl->base + ETH_MODE); + val =3D readb(pctrl->base + oen_offset); if (oen) val &=3D ~BIT(bit); else val |=3D BIT(bit); - writeb(val, pctrl->base + ETH_MODE); + writeb(val, pctrl->base + oen_offset); spin_unlock_irqrestore(&pctrl->lock, flags); =20 return 0; @@ -3164,7 +3167,7 @@ static int rzg2l_pinctrl_suspend_noirq(struct device = *dev) } =20 cache->qspi =3D readb(pctrl->base + QSPI); - cache->eth_mode =3D readb(pctrl->base + ETH_MODE); + cache->eth_mode =3D readb(pctrl->base + pctrl->data->hwcfg->regs.oen); =20 if (!atomic_read(&pctrl->wakeup_path)) clk_disable_unprepare(pctrl->clk); @@ -3189,7 +3192,7 @@ static int rzg2l_pinctrl_resume_noirq(struct device *= dev) } =20 writeb(cache->qspi, pctrl->base + QSPI); - writeb(cache->eth_mode, pctrl->base + ETH_MODE); + writeb(cache->eth_mode, pctrl->base + pctrl->data->hwcfg->regs.oen); for (u8 i =3D 0; i < 2; i++) { if (regs->sd_ch) writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i)); @@ -3241,6 +3244,7 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg =3D { .pwpr =3D 0x3014, .sd_ch =3D 0x3000, .eth_poc =3D 0x300c, + .oen =3D 0x3018, }, .iolh_groupa_ua =3D { /* 3v3 power source */ @@ -3256,6 +3260,7 @@ static const struct rzg2l_hwcfg rzg3s_hwcfg =3D { .pwpr =3D 0x3000, .sd_ch =3D 0x3004, .eth_poc =3D 0x3010, + .oen =3D 0x3018, }, .iolh_groupa_ua =3D { /* 1v8 power source */ --=20 2.49.0