.../bindings/pci/brcm,stb-pcie.yaml | 1 + drivers/pci/controller/pcie-brcmstb.c | 80 ++++++++++++++++++- 2 files changed, 80 insertions(+), 1 deletion(-)
This series enables a new SoC to run with the existing Brcm STB PCIe
driver. Previous chips all required that an inbound window have a size
that is a power of two; this chip, and next generations chips like it, can
have windows of any reasonable size.
Note: This series must follow the commits of two previous and pending
series [1,2].
[1] https://lore.kernel.org/linux-pci/20250613220843.698227-1-james.quinlan@broadcom.com/
[2] https://lore.kernel.org/linux-pci/20250609221710.10315-1-james.quinlan@broadcom.com/
Jim Quinlan (3):
dt-bindings: PCI: brcm,stb-pcie: Add 74110 SoC
PCI: brcmstb: Acommodate newer SOCs with next-gen PCIe inbound mapping
PCI: brcmstb: Add 74110a0 SoC configuration details
.../bindings/pci/brcm,stb-pcie.yaml | 1 +
drivers/pci/controller/pcie-brcmstb.c | 80 ++++++++++++++++++-
2 files changed, 80 insertions(+), 1 deletion(-)
base-commit: 17bbde2e1716e2ee4b997d476b48ae85c5a47671
prerequisite-patch-id: 82aa80f7ebaa1ee1d48b59bd7f1eb6b21db3c41d
prerequisite-patch-id: e7b6b6e618ee225c9f4892a6078e7b3c4f8b1c73
prerequisite-patch-id: 66cabe0efb02132ce7cf8a849b5bb7f19ab407a2
prerequisite-patch-id: 118fda1b363bc18ef0736f917d1dd5497699156e
prerequisite-patch-id: a48573e6eca090a032c0932ff89f26eae4162db8
--
2.34.1
On Thu, Jul 03, 2025 at 05:53:10PM GMT, Jim Quinlan wrote: > This series enables a new SoC to run with the existing Brcm STB PCIe > driver. Previous chips all required that an inbound window have a size > that is a power of two; this chip, and next generations chips like it, can > have windows of any reasonable size. > > Note: This series must follow the commits of two previous and pending > series [1,2]. > > [1] https://lore.kernel.org/linux-pci/20250613220843.698227-1-james.quinlan@broadcom.com/ > [2] https://lore.kernel.org/linux-pci/20250609221710.10315-1-james.quinlan@broadcom.com/ Have you considered my comment on this series? https://lore.kernel.org/linux-pci/a2ebnh3hmcbd5zr545cwu7bcbv6xbhvv7qnsjzovqbkar5apak@kviufeyk5ssr/ - Mani -- மணிவண்ணன் சதாசிவம்
On Tue, Aug 19, 2025 at 10:51 AM Manivannan Sadhasivam <mani@kernel.org> wrote: > > On Thu, Jul 03, 2025 at 05:53:10PM GMT, Jim Quinlan wrote: > > This series enables a new SoC to run with the existing Brcm STB PCIe > > driver. Previous chips all required that an inbound window have a size > > that is a power of two; this chip, and next generations chips like it, can > > have windows of any reasonable size. > > > > Note: This series must follow the commits of two previous and pending > > series [1,2]. > > > > [1] https://lore.kernel.org/linux-pci/20250613220843.698227-1-james.quinlan@broadcom.com/ > > [2] https://lore.kernel.org/linux-pci/20250609221710.10315-1-james.quinlan@broadcom.com/ > > Have you considered my comment on this series? > https://lore.kernel.org/linux-pci/a2ebnh3hmcbd5zr545cwu7bcbv6xbhvv7qnsjzovqbkar5apak@kviufeyk5ssr/ Hi Mani, I'm sorry, I thought I replied to this but obviously I did not. Your points are valid. Our PCIe HW block keeps on mutating, and each time it does we add new code that is triggered off of the soc_base config setting. The end result is not easy on the eyes. I also have submitted the series "PCI: brcmstb: Include cable-modem SoCs". I don't think it has review comments yet, but I am guessing that you will make the same points. So it looks like what you are asking for is a refactoring of the driver and, AFAICT, I need to first submit separate series that does this before submitting the this and the cable modem submission. Do you agree with that? Regards, Jim Quinlan Broadcom STB/CM > > - Mani > > -- > மணிவண்ணன் சதாசிவம்
On Wed, Aug 20, 2025 at 01:08:41PM GMT, Jim Quinlan wrote: > On Tue, Aug 19, 2025 at 10:51 AM Manivannan Sadhasivam <mani@kernel.org> wrote: > > > > On Thu, Jul 03, 2025 at 05:53:10PM GMT, Jim Quinlan wrote: > > > This series enables a new SoC to run with the existing Brcm STB PCIe > > > driver. Previous chips all required that an inbound window have a size > > > that is a power of two; this chip, and next generations chips like it, can > > > have windows of any reasonable size. > > > > > > Note: This series must follow the commits of two previous and pending > > > series [1,2]. > > > > > > [1] https://lore.kernel.org/linux-pci/20250613220843.698227-1-james.quinlan@broadcom.com/ > > > [2] https://lore.kernel.org/linux-pci/20250609221710.10315-1-james.quinlan@broadcom.com/ > > > > Have you considered my comment on this series? > > https://lore.kernel.org/linux-pci/a2ebnh3hmcbd5zr545cwu7bcbv6xbhvv7qnsjzovqbkar5apak@kviufeyk5ssr/ > > Hi Mani, > I'm sorry, I thought I replied to this but obviously I did not. > No issues! > Your points are valid. Our PCIe HW block keeps on mutating, and each > time it does we add new code that is triggered off of the soc_base > config setting. The end result is not easy on the eyes. > > I also have submitted the series "PCI: brcmstb: Include cable-modem > SoCs". I don't think it has review comments yet, but I am guessing > that you will make the same points. > Yes. I intentionally didn't give any comments or merge it since I have the same refactoring comments. > So it looks like what you are asking for is a refactoring of the > driver and, AFAICT, I need to first submit separate series that does > this before submitting the this and the cable modem submission. Do > you agree with that? > Yes, I agree. Refactoring will make life easier for both you and me :) - Mani -- மணிவண்ணன் சதாசிவம்
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