Add device tree support for the Black Sesame Technologies (BST) C1200
CDCU1.0 ADAS 4C2G platform. This platform is based on the BST C1200 SoC
family.
The changes include:
- Adding a new BST device tree directory
- Adding Makefile entries to build the BST platform device trees
- Adding the device tree for the BST C1200 CDCU1.0 ADAS 4C2G board
This board features a quad-core Cortex-A78 CPU, and various peripherals
including UART, MMC, watchdog timer, and interrupt controller.
---
Changes for v2:
1. Reorganized memory map into discrete regions
2. Updated MMC controller definition:
- Split into core/CRM register regions
- Removed deprecated properties
- Updated compatible string
3. Standardized interrupt definitions and numeric formats
4. Removed reserved-memory node (superseded by bounce buffers)
5. Added root compatible string for platform identification
6. Add soc defconfig
Signed-off-by: Ge Gordon <gordon.ge@bst.ai>
Signed-off-by: Albert Yang <yangzh0906@thundersoft.com>
---
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/bst/Makefile | 2 +
.../dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts | 60 +++++++++
arch/arm64/boot/dts/bst/bstc1200.dtsi | 117 ++++++++++++++++++
arch/arm64/configs/defconfig | 1 +
5 files changed, 181 insertions(+)
create mode 100644 arch/arm64/boot/dts/bst/Makefile
create mode 100644 arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts
create mode 100644 arch/arm64/boot/dts/bst/bstc1200.dtsi
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 79b73a21ddc2..a39b6cafb644 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -12,6 +12,7 @@ subdir-y += arm
subdir-y += bitmain
subdir-y += blaize
subdir-y += broadcom
+subdir-y += bst
subdir-y += cavium
subdir-y += exynos
subdir-y += freescale
diff --git a/arch/arm64/boot/dts/bst/Makefile b/arch/arm64/boot/dts/bst/Makefile
new file mode 100644
index 000000000000..4c1b8b4cdad8
--- /dev/null
+++ b/arch/arm64/boot/dts/bst/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_BST) += bstc1200-cdcu1.0-adas_4c2g.dtb
diff --git a/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts b/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts
new file mode 100644
index 000000000000..4036e0ac2e1d
--- /dev/null
+++ b/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "bstc1200.dtsi"
+
+/ {
+ model = "BST C1200-96 CDCU1.0 4C2G";
+ compatible = "bst,c1200-cdcu1.0-adas-4c2g", "bst,c1200";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@810000000 {
+ device_type = "memory";
+ reg = <0x8 0x10000000 0x0 0x30000000>;
+ };
+
+ memory@8c0000000 {
+ device_type = "memory";
+ reg = <0x8 0xc0000000 0x1 0x0>;
+ };
+
+ memory@c00000000 {
+ device_type = "memory";
+ reg = <0xc 0x0 0x0 0x40000000>;
+ };
+
+ memory@800254000 {
+ device_type = "memory";
+ reg = <0x8 0x254000 0x0 0x1000>;
+ };
+
+ memory@800151000 {
+ device_type = "memory";
+ reg = <0x8 0x151000 0x0 0x1000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ mmc0_reserved: mmc0@5160000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x5160000 0x0 0x10000>;
+ no-map;
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&mmc0 {
+ status = "okay";
+ memory-region = <&mmc0_reserved>;
+};
+
diff --git a/arch/arm64/boot/dts/bst/bstc1200.dtsi b/arch/arm64/boot/dts/bst/bstc1200.dtsi
new file mode 100644
index 000000000000..ddff2cb82cb0
--- /dev/null
+++ b/arch/arm64/boot/dts/bst/bstc1200.dtsi
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "bst,c1200";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a78";
+ device_type = "cpu";
+ enable-method = "psci";
+ next-level-cache = <&l2_cache>;
+ reg = <0>;
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a78";
+ device_type = "cpu";
+ enable-method = "psci";
+ next-level-cache = <&l2_cache>;
+ reg = <0x100>;
+ };
+
+ cpu@2 {
+ compatible = "arm,cortex-a78";
+ device_type = "cpu";
+ enable-method = "psci";
+ next-level-cache = <&l2_cache>;
+ reg = <0x200>;
+ };
+
+ cpu@3 {
+ compatible = "arm,cortex-a78";
+ device_type = "cpu";
+ enable-method = "psci";
+ next-level-cache = <&l2_cache>;
+ reg = <0x300>;
+ };
+
+ l2_cache: l2-cache-1 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ };
+ };
+
+ clk_mmc: clock-4000000 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <4000000>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ always-on;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ soc: soc@0 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0x0 0xffffffff 0xffffffff>;
+ interrupt-parent = <&gic>;
+
+ mmc0: mmc@22200000 {
+ compatible = "bst,c1200-dwcmshc-sdhci";
+ reg = <0x0 0x22200000 0x0 0x1000>,
+ <0x0 0x23006000 0x0 0x1000>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_mmc>;
+ clock-names = "core";
+ max-frequency = <200000000>;
+ bus-width = <8>;
+ non-removable;
+ dma-coherent;
+ status = "disabled";
+ };
+
+ uart0: serial@20008000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x20008000 0x0 0x1000>;
+ interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <25000000>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@32800000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-controller;
+ ranges;
+ reg = <0x0 0x32800000 0x0 0x10000>,
+ <0x0 0x32880000 0x0 0x100000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+};
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 897fc686e6a9..0a1cfaa19688 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -45,6 +45,7 @@ CONFIG_ARCH_BCMBCA=y
CONFIG_ARCH_BRCMSTB=y
CONFIG_ARCH_BERLIN=y
CONFIG_ARCH_BLAIZE=y
+CONFIG_ARCH_BST=y
CONFIG_ARCH_EXYNOS=y
CONFIG_ARCH_SPARX5=y
CONFIG_ARCH_K3=y
--
2.25.1On 2025-07-02 10:44 am, Albert Yang wrote:
[...]
> diff --git a/arch/arm64/boot/dts/bst/bstc1200.dtsi b/arch/arm64/boot/dts/bst/bstc1200.dtsi
> new file mode 100644
> index 000000000000..ddff2cb82cb0
> --- /dev/null
> +++ b/arch/arm64/boot/dts/bst/bstc1200.dtsi
> @@ -0,0 +1,117 @@
> +// SPDX-License-Identifier: GPL-2.0
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> + compatible = "bst,c1200";
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + compatible = "arm,cortex-a78";
> + device_type = "cpu";
> + enable-method = "psci";
> + next-level-cache = <&l2_cache>;
> + reg = <0>;
> + };
> +
> + cpu@1 {
> + compatible = "arm,cortex-a78";
> + device_type = "cpu";
> + enable-method = "psci";
> + next-level-cache = <&l2_cache>;
> + reg = <0x100>;
> + };
> +
> + cpu@2 {
> + compatible = "arm,cortex-a78";
> + device_type = "cpu";
> + enable-method = "psci";
> + next-level-cache = <&l2_cache>;
> + reg = <0x200>;
> + };
> +
> + cpu@3 {
> + compatible = "arm,cortex-a78";
> + device_type = "cpu";
> + enable-method = "psci";
> + next-level-cache = <&l2_cache>;
> + reg = <0x300>;
> + };
> +
> + l2_cache: l2-cache-1 {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-unified;
> + };
> + };
> +
> + clk_mmc: clock-4000000 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <4000000>;
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupt-parent = <&gic>;
> + always-on;
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
Your PPIs target 8 of the 4 CPUS? Either way you don't have GICv2,
please use the GICv3 binding.
> + };
> +
> + soc: soc@0 {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0x0 0x0 0x0 0x0 0xffffffff 0xffffffff>;
> + interrupt-parent = <&gic>;
> +
> + mmc0: mmc@22200000 {
> + compatible = "bst,c1200-dwcmshc-sdhci";
> + reg = <0x0 0x22200000 0x0 0x1000>,
> + <0x0 0x23006000 0x0 0x1000>;
> + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk_mmc>;
> + clock-names = "core";
> + max-frequency = <200000000>;
> + bus-width = <8>;
> + non-removable;
> + dma-coherent;
Given the funky DMA setup, I can't help be mildly suspicious of this -
is the device genuinely I/O coherent and capable of snooping the CPU
caches, or are you only getting away with it because
dma_init_coherent_memory() happens to remap as non-cacheable regardless?
Thanks,
Robin.
> + status = "disabled";
> + };
> +
> + uart0: serial@20008000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x20008000 0x0 0x1000>;
> + interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
> + clock-frequency = <25000000>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + gic: interrupt-controller@32800000 {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <3>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + interrupt-controller;
> + ranges;
> + reg = <0x0 0x32800000 0x0 0x10000>,
> + <0x0 0x32880000 0x0 0x100000>;
> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
> + };
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +};
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index 897fc686e6a9..0a1cfaa19688 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -45,6 +45,7 @@ CONFIG_ARCH_BCMBCA=y
> CONFIG_ARCH_BRCMSTB=y
> CONFIG_ARCH_BERLIN=y
> CONFIG_ARCH_BLAIZE=y
> +CONFIG_ARCH_BST=y
> CONFIG_ARCH_EXYNOS=y
> CONFIG_ARCH_SPARX5=y
> CONFIG_ARCH_K3=y
On 02/07/2025 11:44, Albert Yang wrote:
> Add device tree support for the Black Sesame Technologies (BST) C1200
> CDCU1.0 ADAS 4C2G platform. This platform is based on the BST C1200 SoC
> family.
>
> The changes include:
> - Adding a new BST device tree directory
> - Adding Makefile entries to build the BST platform device trees
> - Adding the device tree for the BST C1200 CDCU1.0 ADAS 4C2G board
>
> This board features a quad-core Cortex-A78 CPU, and various peripherals
> including UART, MMC, watchdog timer, and interrupt controller.
>
> ---
> Changes for v2:
> 1. Reorganized memory map into discrete regions
> 2. Updated MMC controller definition:
> - Split into core/CRM register regions
> - Removed deprecated properties
> - Updated compatible string
> 3. Standardized interrupt definitions and numeric formats
> 4. Removed reserved-memory node (superseded by bounce buffers)
> 5. Added root compatible string for platform identification
> 6. Add soc defconfig
>
> Signed-off-by: Ge Gordon <gordon.ge@bst.ai>
> Signed-off-by: Albert Yang <yangzh0906@thundersoft.com>
This is messed. SoB does not go to changelog. Apply your patch and look
at result - do you see SoB? No, because changelog is stripped.
submitting patches explains how this is supposed to look like.
> ---
> arch/arm64/boot/dts/Makefile | 1 +
> arch/arm64/boot/dts/bst/Makefile | 2 +
> .../dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts | 60 +++++++++
> arch/arm64/boot/dts/bst/bstc1200.dtsi | 117 ++++++++++++++++++
> arch/arm64/configs/defconfig | 1 +
> 5 files changed, 181 insertions(+)
> create mode 100644 arch/arm64/boot/dts/bst/Makefile
> create mode 100644 arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts
> create mode 100644 arch/arm64/boot/dts/bst/bstc1200.dtsi
>
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index 79b73a21ddc2..a39b6cafb644 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -12,6 +12,7 @@ subdir-y += arm
> subdir-y += bitmain
> subdir-y += blaize
> subdir-y += broadcom
> +subdir-y += bst
> subdir-y += cavium
> subdir-y += exynos
> subdir-y += freescale
> diff --git a/arch/arm64/boot/dts/bst/Makefile b/arch/arm64/boot/dts/bst/Makefile
> new file mode 100644
> index 000000000000..4c1b8b4cdad8
> --- /dev/null
> +++ b/arch/arm64/boot/dts/bst/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_BST) += bstc1200-cdcu1.0-adas_4c2g.dtb
> diff --git a/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts b/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts
> new file mode 100644
> index 000000000000..4036e0ac2e1d
> --- /dev/null
> +++ b/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts
> @@ -0,0 +1,60 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/dts-v1/;
> +
> +#include "bstc1200.dtsi"
> +
> +/ {
> + model = "BST C1200-96 CDCU1.0 4C2G";
> + compatible = "bst,c1200-cdcu1.0-adas-4c2g", "bst,c1200";
It does not look like you tested the DTS against bindings. Please run
`make dtbs_check W=1` (see
Documentation/devicetree/bindings/writing-schema.rst or
https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/
for instructions).
Maybe you need to update your dtschema and yamllint. Don't rely on
distro packages for dtschema and be sure you are using the latest
released dtschema.
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + memory@810000000 {
> + device_type = "memory";
> + reg = <0x8 0x10000000 0x0 0x30000000>;
> + };
> +
> + memory@8c0000000 {
> + device_type = "memory";
> + reg = <0x8 0xc0000000 0x1 0x0>;
> + };
> +
> + memory@c00000000 {
> + device_type = "memory";
> + reg = <0xc 0x0 0x0 0x40000000>;
> + };
> +
> + memory@800254000 {
> + device_type = "memory";
> + reg = <0x8 0x254000 0x0 0x1000>;
> + };
> +
> + memory@800151000 {
> + device_type = "memory";
> + reg = <0x8 0x151000 0x0 0x1000>;
> + };
Why do you have multiple memory nodes, not one?
Also, why aren't these sorted according to DTS coding style?
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + mmc0_reserved: mmc0@5160000 {
> + compatible = "shared-dma-pool";
> + reg = <0x0 0x5160000 0x0 0x10000>;
> + no-map;
> + };
> + };
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> +
> +&mmc0 {
> + status = "okay";
> + memory-region = <&mmc0_reserved>;
> +};
> +
> diff --git a/arch/arm64/boot/dts/bst/bstc1200.dtsi b/arch/arm64/boot/dts/bst/bstc1200.dtsi
> new file mode 100644
> index 000000000000..ddff2cb82cb0
> --- /dev/null
> +++ b/arch/arm64/boot/dts/bst/bstc1200.dtsi
> @@ -0,0 +1,117 @@
> +// SPDX-License-Identifier: GPL-2.0
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> + compatible = "bst,c1200";
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + compatible = "arm,cortex-a78";
> + device_type = "cpu";
> + enable-method = "psci";
> + next-level-cache = <&l2_cache>;
> + reg = <0>;
> + };
> +
> + cpu@1 {
> + compatible = "arm,cortex-a78";
> + device_type = "cpu";
> + enable-method = "psci";
> + next-level-cache = <&l2_cache>;
> + reg = <0x100>;
Nothing improved. I asked to follow DTS coding style in ordering.
It does not look like you tested the DTS against bindings. Please run
`make dtbs_check W=1` (see
Documentation/devicetree/bindings/writing-schema.rst or
https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/
for instructions).
Maybe you need to update your dtschema and yamllint. Don't rely on
distro packages for dtschema and be sure you are using the latest
released dtschema.
You already got this comment. How did you resolve it? You never
responded to comments, so does it mean you just ignored it or something
was not clear? In any case, repeating the same mistake is not getting
this code merged, so respond to comment.
> + };
> +
> + cpu@2 {
> + compatible = "arm,cortex-a78";
> + device_type = "cpu";
> + enable-method = "psci";
> + next-level-cache = <&l2_cache>;
> + reg = <0x200>;
> + };
> +
> + cpu@3 {
> + compatible = "arm,cortex-a78";
> + device_type = "cpu";
> + enable-method = "psci";
> + next-level-cache = <&l2_cache>;
> + reg = <0x300>;
> + };
> +
> + l2_cache: l2-cache-1 {
l2-cache. Otherwise it is incomplete, so add the second one.
> + compatible = "cache";
> + cache-level = <2>;
> + cache-unified;
> + };
> + };
> +
> + clk_mmc: clock-4000000 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <4000000>;
> + };
> +
> + timer {
t > s
> + compatible = "arm,armv8-timer";
> + interrupt-parent = <&gic>;
> + always-on;
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
> + };
> +
> + soc: soc@0 {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0x0 0x0 0x0 0x0 0xffffffff 0xffffffff>;
Nothing improved. I asked to follow DTS coding style in ordering.
> + interrupt-parent = <&gic>;
> +
> + mmc0: mmc@22200000 {
> + compatible = "bst,c1200-dwcmshc-sdhci";
> + reg = <0x0 0x22200000 0x0 0x1000>,
> + <0x0 0x23006000 0x0 0x1000>;
> + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk_mmc>;
> + clock-names = "core";
> + max-frequency = <200000000>;
> + bus-width = <8>;
> + non-removable;
> + dma-coherent;
> + status = "disabled";
> + };
> +
> + uart0: serial@20008000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x20008000 0x0 0x1000>;
> + interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
> + clock-frequency = <25000000>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + gic: interrupt-controller@32800000 {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <3>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + interrupt-controller;
> + ranges;
> + reg = <0x0 0x32800000 0x0 0x10000>,
> + <0x0 0x32880000 0x0 0x100000>;
Nothing improved. I asked to follow DTS coding style in ordering.
> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
> + };
> + };
> +
> + psci {
p < s, it is really randomly put :/
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +};
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index 897fc686e6a9..0a1cfaa19688 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
This is not a DTS patch.
> @@ -45,6 +45,7 @@ CONFIG_ARCH_BCMBCA=y
> CONFIG_ARCH_BRCMSTB=y
> CONFIG_ARCH_BERLIN=y
> CONFIG_ARCH_BLAIZE=y
> +CONFIG_ARCH_BST=y
> CONFIG_ARCH_EXYNOS=y
> CONFIG_ARCH_SPARX5=y
> CONFIG_ARCH_K3=y
Best regards,
Krzysztof
Hi Krzysztof,
Thank you for your detailed review and feedback. I have addressed all the issues you mentioned:
> This is messed. SoB does not go to changelog. Apply your patch and look
> at result - do you see SoB? No, because changelog is stripped.
> submitting patches explains how this is supposed to look like.
Fixed. Moved Signed-off-by lines to the correct position in commit message,
outside of the changelog section.
> Nothing improved. I asked to follow DTS coding style in ordering.
Fixed. Reordered all nodes according to DTS coding style:
- Root level nodes: alphabetically ordered (clk_mmc → cpus → psci → soc → timer)
- SoC nodes: ordered by address (uart0@20008000 → mmc0@22200000 → gic@32800000)
- Applied consistent ordering throughout the dtsi file
> l2-cache. Otherwise it is incomplete, so add the second one.
Fixed. Renamed l2-cache-1 to l2-cache as per standard naming convention.
> Why do you have multiple memory nodes, not one?
Fixed. Consolidated multiple memory nodes into a single memory node with
multiple reg entries as required by Device Tree specification:
Before (incorrect):
memory@800151000 { reg = <0x8 0x00151000 0x0 0x1000>; };
memory@800254000 { reg = <0x8 0x00254000 0x0 0x1000>; };
...
After (correct):
memory@800151000 {
reg = <0x8 0x00151000 0x0 0x1000>,
<0x8 0x00254000 0x0 0x1000>,
<0x8 0x10000000 0x0 0x30000000>,
<0x8 0xc0000000 0x1 0x0>,
<0xc 0x00000000 0x0 0x40000000>;
};
> It does not look like you tested the DTS against bindings. Please run
> `make dtbs_check W=1`
Fixed. Ran `make dtbs_check W=1` and verified no schema violations.
DTB builds successfully without warnings.
> This is not a DTS patch. (regarding defconfig)
Fixed. Moved all defconfig changes to a separate dedicated commit as suggested.
The DTS commit now only contains device tree related changes.
Additionally, I have addressed all feedback from the v1 review:
- Fixed reserved-memory node naming (mmc0-reserved@5160000)
- Corrected all property ordering according to DTS coding style
- Ensured all nodes follow standard naming conventions
All changes have been tested with:
- make ARCH=arm64 bst/bstc1200-cdcu1.0-adas_4c2g.dtb W=1 (successful)
- DTB validation passes without errors
I will send v3 with all these fixes applied.
Best regards,
Albert Yang
On Wed, Jul 02, 2025 at 08:31:33PM +0800, Albert Yang wrote:
> Hi Krzysztof,
>
> Thank you for your detailed review and feedback. I have addressed all the issues you mentioned:
>
> > This is messed. SoB does not go to changelog. Apply your patch and look
> > at result - do you see SoB? No, because changelog is stripped.
> > submitting patches explains how this is supposed to look like.
>
> Fixed. Moved Signed-off-by lines to the correct position in commit message,
> outside of the changelog section.
>
> > Nothing improved. I asked to follow DTS coding style in ordering.
>
> Fixed. Reordered all nodes according to DTS coding style:
> - Root level nodes: alphabetically ordered (clk_mmc → cpus → psci → soc → timer)
> - SoC nodes: ordered by address (uart0@20008000 → mmc0@22200000 → gic@32800000)
> - Applied consistent ordering throughout the dtsi file
>
> > l2-cache. Otherwise it is incomplete, so add the second one.
>
> Fixed. Renamed l2-cache-1 to l2-cache as per standard naming convention.
>
> > Why do you have multiple memory nodes, not one?
>
> Fixed. Consolidated multiple memory nodes into a single memory node with
> multiple reg entries as required by Device Tree specification:
>
> Before (incorrect):
> memory@800151000 { reg = <0x8 0x00151000 0x0 0x1000>; };
> memory@800254000 { reg = <0x8 0x00254000 0x0 0x1000>; };
> ...
>
> After (correct):
> memory@800151000 {
> reg = <0x8 0x00151000 0x0 0x1000>,
> <0x8 0x00254000 0x0 0x1000>,
These are very odd. Are these really main memory vs. some on chip SRAM
or some other specific purpose?
A 4KB block doesn't really work if the OS uses 16 or 64KB pages, but I
guess that would be up to the OS to ignore them.
> <0x8 0x10000000 0x0 0x30000000>,
> <0x8 0xc0000000 0x1 0x0>,
> <0xc 0x00000000 0x0 0x40000000>;
> };
On Wed, Jul 02, 2025 at 09:19:57AM -0500, Rob Herring wrote:
> On Wed, Jul 02, 2025 at 08:31:33PM +0800, Albert Yang wrote:
> > Before (incorrect):
> > memory@800151000 { reg = <0x8 0x00151000 0x0 0x1000>; };
> > memory@800254000 { reg = <0x8 0x00254000 0x0 0x1000>; };
> > ...
> >
> > After (correct):
> > memory@800151000 {
> > reg = <0x8 0x00151000 0x0 0x1000>,
> > <0x8 0x00254000 0x0 0x1000>,
>
> These are very odd. Are these really main memory vs. some on chip SRAM
> or some other specific purpose?
>
> A 4KB block doesn't really work if the OS uses 16 or 64KB pages, but I
> guess that would be up to the OS to ignore them.
Thank you for pointing out this issue. My colleagues and I have discussed
that these two 4ks are indeed ineffective, so we will remove them in v3
Best Regards,
Albert
On Wed, Jul 02, 2025 at 01:15:13PM +0100, Robin Murphy wrote:
> On 2025-07-02 10:44 am, Albert Yang wrote:
> > + timer {
> > + compatible = "arm,armv8-timer";
> > + interrupt-parent = <&gic>;
> > + always-on;
> > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
>
> Your PPIs target 8 of the 4 CPUS? Either way you don't have GICv2, please
> use the GICv3 binding.
Thank you for pointing out the issue. The mask has been removed according to the GIC v3
format.
>
> > + mmc0: mmc@22200000 {
> > + compatible = "bst,c1200-dwcmshc-sdhci";
> > + reg = <0x0 0x22200000 0x0 0x1000>,
> > + <0x0 0x23006000 0x0 0x1000>;
> > + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk_mmc>;
> > + clock-names = "core";
> > + max-frequency = <200000000>;
> > + bus-width = <8>;
> > + non-removable;
> > + dma-coherent;
>
> Given the funky DMA setup, I can't help be mildly suspicious of this - is
> the device genuinely I/O coherent and capable of snooping the CPU caches, or
> are you only getting away with it because dma_init_coherent_memory() happens
> to remap as non-cacheable regardless?
We allocated a portion of SRAM to serve as a bounce buffer. This buffer is incorporated
into the system's CMA (Contiguous Memory Allocator) framework through a shared DMA mechanism
and requires memory coherency.
Best Regards,
Albert
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