From nobody Wed Oct 8 05:46:25 2025 Received: from mail-m32100.qiye.163.com (mail-m32100.qiye.163.com [220.197.32.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC042221F37; Wed, 2 Jul 2025 11:02:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.32.100 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751454138; cv=none; b=uoVFCsf5AwTp0HWtQ86fuFnErh1VYd/h5601xhZfYPtkw5Bh3ffXGIjkMTQNSBirpixyzHxZUdBBDh0P6kg6C3PiHknn7qoUWgCj9PXCsw+jTIWzjZWzipVAFuGPm96sF4aBRqfydSV+v6UgH8gReiM6RTSVUvboFZ+SL+3Z4og= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751454138; c=relaxed/simple; bh=kgU0nR5T2dnMIfBxf0LYdE0M+4042kRTIUsHe+PjCFY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=RX7zeibFjxe+9+Ip4g4tVWzkriTa6aI81CijAwE5dhWwd1Bq1G+C8zFbRRBYJqcKA+TBB6uk2/K/cqYYXyhitrbW0aDgGLn4AuIUXx+v8NV0oFw/CvdJhr+aEwu6hIxz59vrUN4xzBtdSA5SmP8iqOq2GyTzcnmOi3ebAaGL7Do= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=thundersoft.com; spf=pass smtp.mailfrom=thundersoft.com; dkim=pass (1024-bit key) header.d=thundersoft.com header.i=@thundersoft.com header.b=LcD177pC; arc=none smtp.client-ip=220.197.32.100 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=thundersoft.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=thundersoft.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=thundersoft.com header.i=@thundersoft.com header.b="LcD177pC" Received: from localhost.localdomain (unknown [117.184.129.134]) by smtp.qiye.163.com (Hmail) with ESMTP id 1aaa9ed5f; Wed, 2 Jul 2025 17:46:39 +0800 (GMT+08:00) From: Albert Yang To: robh@kernel.org, krzk+dt@kernel.org, krzk@kernel.org, conor+dt@kernel.org, gordon.ge@bst.ai, catalin.marinas@arm.com, geert.uytterhoeven@gmail.com, will@kernel.org, ulf.hansson@linaro.org, adrian.hunter@intel.com, arnd@arndb.de Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mmc@vger.kernel.org, soc@lists.linux.dev, bst-upstream@bstai.top, neil.armstrong@linaro.org, jonathan.cameron@huawei.com, bigfoot@classfun.cn, kever.yang@rock-chips.com, mani@kernel.org, geert+renesas@glider.be, andersson@kernel.org, nm@ti.com, nfraprado@collabora.com, quic_tdas@quicinc.com, ebiggers@google.com, victor.shih@genesyslogic.com.tw, shanchun1218@gmail.com, ben.chuang@genesyslogic.com.tw, Albert Yang Subject: [PATCH v2 6/8] arm64: dts: bst: add support for Black Sesame Technologies C1200 CDCU1.0 board and defconfig Date: Wed, 2 Jul 2025 17:44:42 +0800 Message-Id: <20250702094444.3523973-7-yangzh0906@thundersoft.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250702094444.3523973-1-yangzh0906@thundersoft.com> References: <20250528085403.481055-1-yangzh0906@thundersoft.com> <20250702094444.3523973-1-yangzh0906@thundersoft.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVkZGh1KVhkZSh5IShofGEIZQlYVFAkWGhdVEwETFh oSFyQUDg9ZV1kYEgtZQVlKSkxVSkNPVUpJQlVKSE9ZV1kWGg8SFR0UWUFZT0tIVUpLSUhCS0NVSk tLVUpCWQY+ X-HM-Tid: 0a97ca87fe7709cckunmee1cabff3ebbc1 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6NxQ6FRw6ATE9S082Kxo#HU4K SktPChJVSlVKTE5KT09CTUtKTkhLVTMWGhIXVQIaFRwBE0tCS007DxMOFR8eCQgUHQ9VGBQWRVlX WRILWUFZSkpMVUpDT1VKSUJVSkhPWVdZCAFZQUNOSEg3Bg++ DKIM-Signature: a=rsa-sha256; b=LcD177pCHl9iMO/5tUAt9Aup0ONwc3+JngKUJx11307DXxj7xrMMLTfrkru6dy9fG5OqClUhFsen0OXjZr3TQkj6TkPZbRato/YtS6S3q4HxRwn3mjk/5qP8dqv6YM2UrPx63HayhL6GMD7TkHzCDa5meJI89+FfSMnivNyI5SM=; c=relaxed/relaxed; s=default; d=thundersoft.com; v=1; bh=7zX9xAz2D0jYqJzruhcDB4kWgwhYwe/xmi9zdJYXp4s=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add device tree support for the Black Sesame Technologies (BST) C1200 CDCU1.0 ADAS 4C2G platform. This platform is based on the BST C1200 SoC family. The changes include: - Adding a new BST device tree directory - Adding Makefile entries to build the BST platform device trees - Adding the device tree for the BST C1200 CDCU1.0 ADAS 4C2G board This board features a quad-core Cortex-A78 CPU, and various peripherals including UART, MMC, watchdog timer, and interrupt controller. --- Changes for v2: 1. Reorganized memory map into discrete regions 2. Updated MMC controller definition: - Split into core/CRM register regions - Removed deprecated properties - Updated compatible string 3. Standardized interrupt definitions and numeric formats 4. Removed reserved-memory node (superseded by bounce buffers) 5. Added root compatible string for platform identification 6. Add soc defconfig Signed-off-by: Ge Gordon Signed-off-by: Albert Yang --- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/bst/Makefile | 2 + .../dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts | 60 +++++++++ arch/arm64/boot/dts/bst/bstc1200.dtsi | 117 ++++++++++++++++++ arch/arm64/configs/defconfig | 1 + 5 files changed, 181 insertions(+) create mode 100644 arch/arm64/boot/dts/bst/Makefile create mode 100644 arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts create mode 100644 arch/arm64/boot/dts/bst/bstc1200.dtsi diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 79b73a21ddc2..a39b6cafb644 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -12,6 +12,7 @@ subdir-y +=3D arm subdir-y +=3D bitmain subdir-y +=3D blaize subdir-y +=3D broadcom +subdir-y +=3D bst subdir-y +=3D cavium subdir-y +=3D exynos subdir-y +=3D freescale diff --git a/arch/arm64/boot/dts/bst/Makefile b/arch/arm64/boot/dts/bst/Mak= efile new file mode 100644 index 000000000000..4c1b8b4cdad8 --- /dev/null +++ b/arch/arm64/boot/dts/bst/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_BST) +=3D bstc1200-cdcu1.0-adas_4c2g.dtb diff --git a/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts b/arch/= arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts new file mode 100644 index 000000000000..4036e0ac2e1d --- /dev/null +++ b/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "bstc1200.dtsi" + +/ { + model =3D "BST C1200-96 CDCU1.0 4C2G"; + compatible =3D "bst,c1200-cdcu1.0-adas-4c2g", "bst,c1200"; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + memory@810000000 { + device_type =3D "memory"; + reg =3D <0x8 0x10000000 0x0 0x30000000>; + }; + + memory@8c0000000 { + device_type =3D "memory"; + reg =3D <0x8 0xc0000000 0x1 0x0>; + }; + + memory@c00000000 { + device_type =3D "memory"; + reg =3D <0xc 0x0 0x0 0x40000000>; + }; + + memory@800254000 { + device_type =3D "memory"; + reg =3D <0x8 0x254000 0x0 0x1000>; + }; + + memory@800151000 { + device_type =3D "memory"; + reg =3D <0x8 0x151000 0x0 0x1000>; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + mmc0_reserved: mmc0@5160000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x0 0x5160000 0x0 0x10000>; + no-map; + }; + }; +}; + +&uart0 { + status =3D "okay"; +}; + +&mmc0 { + status =3D "okay"; + memory-region =3D <&mmc0_reserved>; +}; + diff --git a/arch/arm64/boot/dts/bst/bstc1200.dtsi b/arch/arm64/boot/dts/bs= t/bstc1200.dtsi new file mode 100644 index 000000000000..ddff2cb82cb0 --- /dev/null +++ b/arch/arm64/boot/dts/bst/bstc1200.dtsi @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include + +/ { + compatible =3D "bst,c1200"; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu@0 { + compatible =3D "arm,cortex-a78"; + device_type =3D "cpu"; + enable-method =3D "psci"; + next-level-cache =3D <&l2_cache>; + reg =3D <0>; + }; + + cpu@1 { + compatible =3D "arm,cortex-a78"; + device_type =3D "cpu"; + enable-method =3D "psci"; + next-level-cache =3D <&l2_cache>; + reg =3D <0x100>; + }; + + cpu@2 { + compatible =3D "arm,cortex-a78"; + device_type =3D "cpu"; + enable-method =3D "psci"; + next-level-cache =3D <&l2_cache>; + reg =3D <0x200>; + }; + + cpu@3 { + compatible =3D "arm,cortex-a78"; + device_type =3D "cpu"; + enable-method =3D "psci"; + next-level-cache =3D <&l2_cache>; + reg =3D <0x300>; + }; + + l2_cache: l2-cache-1 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + }; + }; + + clk_mmc: clock-4000000 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <4000000>; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupt-parent =3D <&gic>; + always-on; + interrupts =3D , + , + , + ; + }; + + soc: soc@0 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0x0 0x0 0x0 0x0 0xffffffff 0xffffffff>; + interrupt-parent =3D <&gic>; + + mmc0: mmc@22200000 { + compatible =3D "bst,c1200-dwcmshc-sdhci"; + reg =3D <0x0 0x22200000 0x0 0x1000>, + <0x0 0x23006000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&clk_mmc>; + clock-names =3D "core"; + max-frequency =3D <200000000>; + bus-width =3D <8>; + non-removable; + dma-coherent; + status =3D "disabled"; + }; + + uart0: serial@20008000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x0 0x20008000 0x0 0x1000>; + interrupts =3D ; + clock-frequency =3D <25000000>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + gic: interrupt-controller@32800000 { + compatible =3D "arm,gic-v3"; + #interrupt-cells =3D <3>; + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-controller; + ranges; + reg =3D <0x0 0x32800000 0x0 0x10000>, + <0x0 0x32880000 0x0 0x100000>; + interrupts =3D ; + }; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; +}; diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 897fc686e6a9..0a1cfaa19688 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -45,6 +45,7 @@ CONFIG_ARCH_BCMBCA=3Dy CONFIG_ARCH_BRCMSTB=3Dy CONFIG_ARCH_BERLIN=3Dy CONFIG_ARCH_BLAIZE=3Dy +CONFIG_ARCH_BST=3Dy CONFIG_ARCH_EXYNOS=3Dy CONFIG_ARCH_SPARX5=3Dy CONFIG_ARCH_K3=3Dy --=20 2.25.1