Add support for video, camera, display and gpu clock controller nodes
for QCS615 platform.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
---
arch/arm64/boot/dts/qcom/qcs615.dtsi | 51 ++++++++++++++++++++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
index bfbb210354922766a03fe05e6d117ea21d118081..5adf409d7ce7226042c759cc83ceca331097ae37 100644
--- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
@@ -3,7 +3,11 @@
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
+#include <dt-bindings/clock/qcom,qcs615-camcc.h>
+#include <dt-bindings/clock/qcom,qcs615-dispcc.h>
#include <dt-bindings/clock/qcom,qcs615-gcc.h>
+#include <dt-bindings/clock/qcom,qcs615-gpucc.h>
+#include <dt-bindings/clock/qcom,qcs615-videocc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/interconnect/qcom,icc.h>
@@ -1506,6 +1510,18 @@ data-pins {
};
};
+ gpucc: clock-controller@5090000 {
+ compatible = "qcom,qcs615-gpucc";
+ reg = <0 0x05090000 0 0x9000>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GPLL0>;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
stm@6002000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0x0 0x06002000 0x0 0x1000>,
@@ -3317,6 +3333,41 @@ gem_noc: interconnect@9680000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ videocc: clock-controller@ab00000 {
+ compatible = "qcom,qcs615-videocc";
+ reg = <0 0x0ab00000 0 0x10000>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&sleep_clk>;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ camcc: clock-controller@ad00000 {
+ compatible = "qcom,qcs615-camcc";
+ reg = <0 0x0ad00000 0 0x10000>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ dispcc: clock-controller@af00000 {
+ compatible = "qcom,qcs615-dispcc";
+ reg = <0 0x0af00000 0 0x20000>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,qcs615-pdc", "qcom,pdc";
reg = <0x0 0x0b220000 0x0 0x30000>,
--
2.34.1On Wed, Jul 02, 2025 at 02:43:10PM +0530, Taniya Das wrote:
> Add support for video, camera, display and gpu clock controller nodes
> for QCS615 platform.
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> ---
DTC [C] arch/arm64/boot/dts/qcom/qcs615-ride.dtb
/home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@100000: 'clock-names' is a required property
from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-gcc.yaml#
/home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@5090000: clocks: [[43, 0], [45, 2]] is too short
from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-gpucc.yaml#
/home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@5090000: Unevaluated properties are not allowed ('clocks' was unexpected)
from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-gpucc.yaml#
/home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@af00000: clocks: [[43, 0], [45, 29]] is too short
from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-dispcc.yaml#
/home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@af00000: Unevaluated properties are not allowed ('clocks' was unexpected)
from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-dispcc.yaml#
The missing clock-names in clock-controller@100000 predates this series.
Sorry for merging broken patches in the past, please fix that as well.
Regards,
Bjorn
> arch/arm64/boot/dts/qcom/qcs615.dtsi | 51 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 51 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> index bfbb210354922766a03fe05e6d117ea21d118081..5adf409d7ce7226042c759cc83ceca331097ae37 100644
> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> @@ -3,7 +3,11 @@
> * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
> */
>
> +#include <dt-bindings/clock/qcom,qcs615-camcc.h>
> +#include <dt-bindings/clock/qcom,qcs615-dispcc.h>
> #include <dt-bindings/clock/qcom,qcs615-gcc.h>
> +#include <dt-bindings/clock/qcom,qcs615-gpucc.h>
> +#include <dt-bindings/clock/qcom,qcs615-videocc.h>
> #include <dt-bindings/clock/qcom,rpmh.h>
> #include <dt-bindings/dma/qcom-gpi.h>
> #include <dt-bindings/interconnect/qcom,icc.h>
> @@ -1506,6 +1510,18 @@ data-pins {
> };
> };
>
> + gpucc: clock-controller@5090000 {
> + compatible = "qcom,qcs615-gpucc";
> + reg = <0 0x05090000 0 0x9000>;
> +
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GPLL0>;
> +
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + };
> +
> stm@6002000 {
> compatible = "arm,coresight-stm", "arm,primecell";
> reg = <0x0 0x06002000 0x0 0x1000>,
> @@ -3317,6 +3333,41 @@ gem_noc: interconnect@9680000 {
> qcom,bcm-voters = <&apps_bcm_voter>;
> };
>
> + videocc: clock-controller@ab00000 {
> + compatible = "qcom,qcs615-videocc";
> + reg = <0 0x0ab00000 0 0x10000>;
> +
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&sleep_clk>;
> +
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + };
> +
> + camcc: clock-controller@ad00000 {
> + compatible = "qcom,qcs615-camcc";
> + reg = <0 0x0ad00000 0 0x10000>;
> +
> + clocks = <&rpmhcc RPMH_CXO_CLK>;
> +
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + };
> +
> + dispcc: clock-controller@af00000 {
> + compatible = "qcom,qcs615-dispcc";
> + reg = <0 0x0af00000 0 0x20000>;
> +
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
> +
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + };
> +
> pdc: interrupt-controller@b220000 {
> compatible = "qcom,qcs615-pdc", "qcom,pdc";
> reg = <0x0 0x0b220000 0x0 0x30000>,
>
> --
> 2.34.1
>
On 8/12/2025 9:15 AM, Bjorn Andersson wrote:
> On Wed, Jul 02, 2025 at 02:43:10PM +0530, Taniya Das wrote:
>> Add support for video, camera, display and gpu clock controller nodes
>> for QCS615 platform.
>>
>> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>> ---
>
> DTC [C] arch/arm64/boot/dts/qcom/qcs615-ride.dtb
> /home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@100000: 'clock-names' is a required property
> from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-gcc.yaml#
> /home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@5090000: clocks: [[43, 0], [45, 2]] is too short
> from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-gpucc.yaml#
> /home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@5090000: Unevaluated properties are not allowed ('clocks' was unexpected)
> from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-gpucc.yaml#
> /home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@af00000: clocks: [[43, 0], [45, 29]] is too short
> from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-dispcc.yaml#
> /home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@af00000: Unevaluated properties are not allowed ('clocks' was unexpected)
> from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-dispcc.yaml#
>
>
> The missing clock-names in clock-controller@100000 predates this series.
> Sorry for merging broken patches in the past, please fix that as well.
>
Bjorn, would you prefer that I add the clock-names property to the GCC
clock node to resolve the warning, or should I instead remove the
required: clock-names entry from the qcom,qcs615-gcc.yaml schema?
Let me know which approach aligns better with your expectations.
--
Thanks,
Taniya Das
On Tue, Aug 12, 2025 at 02:25:12PM +0530, Taniya Das wrote:
>
>
> On 8/12/2025 9:15 AM, Bjorn Andersson wrote:
> > On Wed, Jul 02, 2025 at 02:43:10PM +0530, Taniya Das wrote:
> >> Add support for video, camera, display and gpu clock controller nodes
> >> for QCS615 platform.
> >>
> >> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> >> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> >> ---
> >
> > DTC [C] arch/arm64/boot/dts/qcom/qcs615-ride.dtb
> > /home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@100000: 'clock-names' is a required property
> > from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-gcc.yaml#
> > /home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@5090000: clocks: [[43, 0], [45, 2]] is too short
> > from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-gpucc.yaml#
> > /home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@5090000: Unevaluated properties are not allowed ('clocks' was unexpected)
> > from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-gpucc.yaml#
> > /home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@af00000: clocks: [[43, 0], [45, 29]] is too short
> > from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-dispcc.yaml#
> > /home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@af00000: Unevaluated properties are not allowed ('clocks' was unexpected)
> > from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-dispcc.yaml#
> >
> >
> > The missing clock-names in clock-controller@100000 predates this series.
> > Sorry for merging broken patches in the past, please fix that as well.
> >
>
> Bjorn, would you prefer that I add the clock-names property to the GCC
> clock node to resolve the warning, or should I instead remove the
> required: clock-names entry from the qcom,qcs615-gcc.yaml schema?
>
It seems to me that the qcs615 gcc binding and driver is lacking a
number of clock inputs. Can you please look into correcting this, and
based on that resolve the dtbs_check error?
Thanks,
Bjorn
> Let me know which approach aligns better with your expectations.
>
> --
> Thanks,
> Taniya Das
>
On 8/13/2025 10:50 PM, Bjorn Andersson wrote:
> On Tue, Aug 12, 2025 at 02:25:12PM +0530, Taniya Das wrote:
>>
>>
>> On 8/12/2025 9:15 AM, Bjorn Andersson wrote:
>>> On Wed, Jul 02, 2025 at 02:43:10PM +0530, Taniya Das wrote:
>>>> Add support for video, camera, display and gpu clock controller nodes
>>>> for QCS615 platform.
>>>>
>>>> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>>>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>>>> ---
>>>
>>> DTC [C] arch/arm64/boot/dts/qcom/qcs615-ride.dtb
>>> /home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@100000: 'clock-names' is a required property
>>> from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-gcc.yaml#
>>> /home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@5090000: clocks: [[43, 0], [45, 2]] is too short
>>> from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-gpucc.yaml#
>>> /home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@5090000: Unevaluated properties are not allowed ('clocks' was unexpected)
>>> from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-gpucc.yaml#
>>> /home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@af00000: clocks: [[43, 0], [45, 29]] is too short
>>> from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-dispcc.yaml#
>>> /home/bjorn/sandbox/kernel/db845c/arch/arm64/boot/dts/qcom/qcs615-ride.dtb: clock-controller@af00000: Unevaluated properties are not allowed ('clocks' was unexpected)
>>> from schema $id: http://devicetree.org/schemas/clock/qcom,qcs615-dispcc.yaml#
>>>
>>>
Bjorn, I will push another series which will fix the above errors.
>>> The missing clock-names in clock-controller@100000 predates this series.
>>> Sorry for merging broken patches in the past, please fix that as well.
>>>
>>
>> Bjorn, would you prefer that I add the clock-names property to the GCC
>> clock node to resolve the warning, or should I instead remove the
>> required: clock-names entry from the qcom,qcs615-gcc.yaml schema?
>>
>
> It seems to me that the qcs615 gcc binding and driver is lacking a
> number of clock inputs. Can you please look into correcting this, and
> based on that resolve the dtbs_check error?
>
>
Yes, Bjorn. I will surely look into to fix them bindings and driver.
>
>> Let me know which approach aligns better with your expectations.
>>
>> --
>> Thanks,
>> Taniya Das
>>
--
Thanks,
Taniya Das
On 7/2/25 11:13 AM, Taniya Das wrote: > Add support for video, camera, display and gpu clock controller nodes > for QCS615 platform. > > Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> > Signed-off-by: Taniya Das <quic_tdas@quicinc.com> > --- Bjorn mentioned offline that these controllers should probably have power-domains attached to them (perhaps bar GPU_CC, that's under discussion..) Konrad
On 7/30/2025 7:07 PM, Konrad Dybcio wrote: > On 7/2/25 11:13 AM, Taniya Das wrote: >> Add support for video, camera, display and gpu clock controller nodes >> for QCS615 platform. >> >> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> >> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> >> --- > > Bjorn mentioned offline that these controllers should > probably have power-domains attached to them (perhaps bar > GPU_CC, that's under discussion..) > The GPU_CC on QCS615 is all on CX and we do not require any power-domain to be attached. -- Taniya.
On 7/30/2025 7:07 PM, Konrad Dybcio wrote: > On 7/2/25 11:13 AM, Taniya Das wrote: >> Add support for video, camera, display and gpu clock controller nodes >> for QCS615 platform. >> >> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> >> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> >> --- > > Bjorn mentioned offline that these controllers should > probably have power-domains attached to them (perhaps bar > GPU_CC, that's under discussion..) QCS615 has an rgmu which doesn't manage gpucc. So this is a different case from the other discussion. Are we talking about scaling mx and cx rail while setting clk rate? Downstream clk driver does that on behalf of the clients. I suppose you are not talking about that here. -Akhil. > > Konrad >
On 7/30/25 6:10 PM, Akhil P Oommen wrote:
> On 7/30/2025 7:07 PM, Konrad Dybcio wrote:
>> On 7/2/25 11:13 AM, Taniya Das wrote:
>>> Add support for video, camera, display and gpu clock controller nodes
>>> for QCS615 platform.
>>>
>>> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>>> ---
>>
>> Bjorn mentioned offline that these controllers should
>> probably have power-domains attached to them (perhaps bar
>> GPU_CC, that's under discussion..)
>
> QCS615 has an rgmu which doesn't manage gpucc. So this is a different
> case from the other discussion. Are we talking about scaling mx and cx
> rail while setting clk rate? Downstream clk driver does that on behalf
> of the clients. I suppose you are not talking about that here.
This is also relevant, as pmdomain states are propagated up the
tree, e.g. if we have:
usb@foobar {
...
power-domains = <&gcc USB30_GDSC>;
};
when someone calls dev_pm_opp_set_level() (or something equivalent like
dev_pm_opp_set_rate() with required-opps defined in the table), it
will set the performance state of the GDSC (which is a NOP for the GDSC
itself), but if we have this hunk:
gcc@feedbeef {
...
power-domains = <&rpmhpd RPMHPD_CX>;
};
RPMHPD_CX will be declared as a parent of all GCC GDSCs and its state
will be altered too. See:
drivers/pmdomain/core.c : _genpd_set_performance_state()
TLDR: clients are responsible for ensuring vdd_levels are set
Konrad
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