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Wysocki" , Viresh Kumar , "Manivannan Sadhasivam" CC: Ajit Pandey , Imran Shaik , Jagadeesh Kona , , , , , Taniya Das , Konrad Dybcio X-Mailer: b4 0.15-dev-aa3f6 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzAyMDA3NCBTYWx0ZWRfX6QjEFwGmv77Q K0zWOUiaBapMDWK0V2Zlz/X5udHF8XnU1Y8y//tYOkkSsk5M3Gt2mdyAaW/8fVOa7InNLnNLP7f LeAKgOyzXg3CYNAtVtlSX6OB9hkdt914evIBWvakBRVKct258uDOfFdDj4JoljcwRFSdQY816KY H/f+oK/EOH600BvERH2LDvjycpt5u5m5mYAN/f3j/L524lx2ndqnQIaJxLXCVTjprWF4hQXPpGd LepdPoPTb8B28ogMwqGyEuixSUdaQ1tRPqfhv1GbTS/AMEiFfXy0L5QPc/Ie5I0laRLGOdIdTig H5+cx9b1k4TzBKKj5WLhmtB3W0HCxR7TAvz1oY4yZIGBPX5ceECUqGh0tK5D0+6FhzQB/8ADMEt iTGM4BHYxQfPGsQ4ZMU6QjtynCScQS6tH2MTZSW1phZ7LMaupbH9KzkqYixVMdxDERgmgBbX X-Authority-Analysis: v=2.4 cv=EbvIQOmC c=1 sm=1 tr=0 ts=6864f842 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=eX7r7zjc-4eniw70hzgA:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: sdsId31KfSQxs9ir6hZ05bmrLtFQY9kG X-Proofpoint-GUID: sdsId31KfSQxs9ir6hZ05bmrLtFQY9kG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-02_01,2025-06-27_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxscore=0 priorityscore=1501 mlxlogscore=999 lowpriorityscore=0 malwarescore=0 adultscore=0 clxscore=1015 bulkscore=0 impostorscore=0 spamscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507020074 Add support for video, camera, display and gpu clock controller nodes for QCS615 platform. Reviewed-by: Konrad Dybcio Signed-off-by: Taniya Das --- arch/arm64/boot/dts/qcom/qcs615.dtsi | 51 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qco= m/qcs615.dtsi index bfbb210354922766a03fe05e6d117ea21d118081..5adf409d7ce7226042c759cc83c= eca331097ae37 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -3,7 +3,11 @@ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. */ =20 +#include +#include #include +#include +#include #include #include #include @@ -1506,6 +1510,18 @@ data-pins { }; }; =20 + gpucc: clock-controller@5090000 { + compatible =3D "qcom,qcs615-gpucc"; + reg =3D <0 0x05090000 0 0x9000>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GPLL0>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + stm@6002000 { compatible =3D "arm,coresight-stm", "arm,primecell"; reg =3D <0x0 0x06002000 0x0 0x1000>, @@ -3317,6 +3333,41 @@ gem_noc: interconnect@9680000 { qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 + videocc: clock-controller@ab00000 { + compatible =3D "qcom,qcs615-videocc"; + reg =3D <0 0x0ab00000 0 0x10000>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + camcc: clock-controller@ad00000 { + compatible =3D "qcom,qcs615-camcc"; + reg =3D <0 0x0ad00000 0 0x10000>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + dispcc: clock-controller@af00000 { + compatible =3D "qcom,qcs615-dispcc"; + reg =3D <0 0x0af00000 0 0x20000>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + pdc: interrupt-controller@b220000 { compatible =3D "qcom,qcs615-pdc", "qcom,pdc"; reg =3D <0x0 0x0b220000 0x0 0x30000>, --=20 2.34.1