arch/arm/boot/dts/renesas/r7s72100-genmai.dts | 3 ++- arch/arm/boot/dts/renesas/r7s72100-gr-peach.dts | 3 ++- arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts | 2 ++ arch/arm/boot/dts/renesas/r7s72100.dtsi | 5 +++++ 4 files changed, 11 insertions(+), 2 deletions(-)
bootph-all as phase tag was added to dt-schema (dtschema/schemas/bootph.yaml)
to describe various node usage during boot phases with DT. Add bootph-all for
all nodes that are used in the bootloader on Renesas RZ/A1 SoC.
All SoC require BSC bus, PFC pin control and OSTM0 timer access during all
stages of the boot process, those are marked using bootph-all property, and
so is the SoC bus node which contains the PFC and OSTM IPs.
Each board console UART is also marked as bootph-all to make it available in
all stages of the boot process.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-renesas-soc@vger.kernel.org
---
arch/arm/boot/dts/renesas/r7s72100-genmai.dts | 3 ++-
arch/arm/boot/dts/renesas/r7s72100-gr-peach.dts | 3 ++-
arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts | 2 ++
arch/arm/boot/dts/renesas/r7s72100.dtsi | 5 +++++
4 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/renesas/r7s72100-genmai.dts b/arch/arm/boot/dts/renesas/r7s72100-genmai.dts
index c81840dfb7da..13c0324b8def 100644
--- a/arch/arm/boot/dts/renesas/r7s72100-genmai.dts
+++ b/arch/arm/boot/dts/renesas/r7s72100-genmai.dts
@@ -258,6 +258,7 @@ mmcif_pins: mmcif {
};
scif2_pins: serial2 {
+ bootph-all;
/* P3_0 as TxD2; P3_2 as RxD2 */
pinmux = <RZA1_PINMUX(3, 0, 6)>, <RZA1_PINMUX(3, 2, 4)>;
};
@@ -286,7 +287,7 @@ &rtc {
&scif2 {
pinctrl-names = "default";
pinctrl-0 = <&scif2_pins>;
-
+ bootph-all;
status = "okay";
};
diff --git a/arch/arm/boot/dts/renesas/r7s72100-gr-peach.dts b/arch/arm/boot/dts/renesas/r7s72100-gr-peach.dts
index 9d29861f23f1..e4f489522b2b 100644
--- a/arch/arm/boot/dts/renesas/r7s72100-gr-peach.dts
+++ b/arch/arm/boot/dts/renesas/r7s72100-gr-peach.dts
@@ -59,6 +59,7 @@ led1 {
&pinctrl {
scif2_pins: serial2 {
+ bootph-all;
/* P6_2 as RxD2; P6_3 as TxD2 */
pinmux = <RZA1_PINMUX(6, 2, 7)>, <RZA1_PINMUX(6, 3, 7)>;
};
@@ -109,7 +110,7 @@ &ostm1 {
&scif2 {
pinctrl-names = "default";
pinctrl-0 = <&scif2_pins>;
-
+ bootph-all;
status = "okay";
};
diff --git a/arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts b/arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts
index 25c6d0c78828..0bf106e9827e 100644
--- a/arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts
+++ b/arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts
@@ -199,6 +199,7 @@ keyboard_pins: keyboard {
/* Serial Console */
scif2_pins: serial2 {
+ bootph-all;
pinmux = <RZA1_PINMUX(3, 0, 6)>, /* TxD2 */
<RZA1_PINMUX(3, 2, 4)>; /* RxD2 */
};
@@ -278,6 +279,7 @@ &rtc {
&scif2 {
pinctrl-names = "default";
pinctrl-0 = <&scif2_pins>;
+ bootph-all;
status = "okay";
};
diff --git a/arch/arm/boot/dts/renesas/r7s72100.dtsi b/arch/arm/boot/dts/renesas/r7s72100.dtsi
index 1a866dbaf5e9..c78131e3cd24 100644
--- a/arch/arm/boot/dts/renesas/r7s72100.dtsi
+++ b/arch/arm/boot/dts/renesas/r7s72100.dtsi
@@ -41,6 +41,7 @@ bsc: bus {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x18000000>;
+ bootph-all;
};
cpus {
@@ -108,6 +109,8 @@ soc {
#size-cells = <1>;
ranges;
+ bootph-all;
+
L2: cache-controller@3ffff000 {
compatible = "arm,pl310-cache";
reg = <0x3ffff000 0x1000>;
@@ -557,6 +560,7 @@ R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11
pinctrl: pinctrl@fcfe3000 {
compatible = "renesas,r7s72100-ports";
+ bootph-all;
reg = <0xfcfe3000 0x4230>;
@@ -639,6 +643,7 @@ ostm0: timer@fcfec000 {
interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
power-domains = <&cpg_clocks>;
+ bootph-all;
status = "disabled";
};
--
2.47.2Hi Marek,
On Mon, 30 Jun 2025 at 00:05, Marek Vasut
<marek.vasut+renesas@mailbox.org> wrote:
> bootph-all as phase tag was added to dt-schema (dtschema/schemas/bootph.yaml)
> to describe various node usage during boot phases with DT. Add bootph-all for
> all nodes that are used in the bootloader on Renesas RZ/A1 SoC.
>
> All SoC require BSC bus, PFC pin control and OSTM0 timer access during all
> stages of the boot process, those are marked using bootph-all property, and
> so is the SoC bus node which contains the PFC and OSTM IPs.
>
> Each board console UART is also marked as bootph-all to make it available in
> all stages of the boot process.
>
> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Thanks for your patch!
> --- a/arch/arm/boot/dts/renesas/r7s72100.dtsi
> +++ b/arch/arm/boot/dts/renesas/r7s72100.dtsi
> @@ -41,6 +41,7 @@ bsc: bus {
> #address-cells = <1>;
> #size-cells = <1>;
> ranges = <0 0 0x18000000>;
> + bootph-all;
> };
>
> cpus {
> @@ -108,6 +109,8 @@ soc {
> #size-cells = <1>;
> ranges;
>
Please drop this blank line.
> + bootph-all;
> +
> L2: cache-controller@3ffff000 {
> compatible = "arm,pl310-cache";
> reg = <0x3ffff000 0x1000>;
> @@ -639,6 +643,7 @@ ostm0: timer@fcfec000 {
> interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
> clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
> power-domains = <&cpg_clocks>;
> + bootph-all;
Please move this to the board-specific .dts files, where this node
is enabled.
> status = "disabled";
> };
>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On 8/6/25 11:11 AM, Geert Uytterhoeven wrote:
> Hi Marek,
Hi,
>> @@ -639,6 +643,7 @@ ostm0: timer@fcfec000 {
>> interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
>> clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
>> power-domains = <&cpg_clocks>;
>> + bootph-all;
>
> Please move this to the board-specific .dts files, where this node
> is enabled.
Shouldn't we rather enable OSTM0 by default , it is enabled in all RZA1
upstream board DTs it seems.
Hi Marek,
On Wed, 6 Aug 2025 at 17:06, Marek Vasut <marek.vasut@mailbox.org> wrote:
> On 8/6/25 11:11 AM, Geert Uytterhoeven wrote:
> >> @@ -639,6 +643,7 @@ ostm0: timer@fcfec000 {
> >> interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
> >> clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
> >> power-domains = <&cpg_clocks>;
> >> + bootph-all;
> >
> > Please move this to the board-specific .dts files, where this node
> > is enabled.
> Shouldn't we rather enable OSTM0 by default , it is enabled in all RZA1
> upstream board DTs it seems.
Perhaps. We used to have issues with enabling all timers by default,
as some may be used by (secure) firmware or another OS.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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