From: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
Update the RSCI binding to support an optional secondary clock input on
the RZ/T2H SoC. At boot, the RSCI operates using the default synchronous
clock (PCLKM core clock), which is enabled by the bootloader. However, to
support a wider range of baud rates, the hardware also requires an
asynchronous external clock input. Clock selection is controlled
internally by the CCR3 register in the RSCI block.
Due to an incomplete understanding of the hardware, the original binding
defined only a single clock ("fck"), which is insufficient to describe the
full capabilities of the RSCI on RZ/T2H. This update corrects the binding
by allowing up to three clocks and defining the `clock-names` as
"operation", "bus", and optionally "sck" for the asynchronous clock input.
This is an ABI change, as it modifies the expected number and names of
clocks. However, since there are no in-kernel consumers of this binding
yet, the change is considered safe and non-disruptive.
Also remove the unneeded `serial0` alias from the DTS example and use
the R9A09G077_CLK_PCLKM macro for core clock.
Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v12->v13:
- Rebased on latest linux-next.
- Updated commit message to clarify the ABI change.
- Used `R9A09G077_CLK_PCLKM` macro for core clock
---
.../bindings/serial/renesas,rsci.yaml | 19 ++++++++++---------
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
index 4aacc44bb509..f80cb60ae099 100644
--- a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
+++ b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
@@ -41,10 +41,15 @@ properties:
- const: tei
clocks:
- maxItems: 1
+ minItems: 2
+ maxItems: 3
clock-names:
- const: fck # UART functional clock
+ minItems: 2
+ items:
+ - const: operation
+ - const: bus
+ - const: sck # optional external clock input
power-domains:
maxItems: 1
@@ -63,12 +68,8 @@ unevaluatedProperties: false
examples:
- |
+ #include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/clock/renesas-cpg-mssr.h>
-
- aliases {
- serial0 = &sci0;
- };
sci0: serial@80005000 {
compatible = "renesas,r9a09g077-rsci";
@@ -78,7 +79,7 @@ examples:
<GIC_SPI 592 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi", "tei";
- clocks = <&cpg CPG_MOD 108>;
- clock-names = "fck";
+ clocks = <&cpg CPG_MOD 8>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
+ clock-names = "operation", "bus";
power-domains = <&cpg>;
};
--
2.49.0Hi Prabhakar,
On Sat, 28 Jun 2025 at 13:57, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
>
> Update the RSCI binding to support an optional secondary clock input on
> the RZ/T2H SoC. At boot, the RSCI operates using the default synchronous
> clock (PCLKM core clock), which is enabled by the bootloader. However, to
> support a wider range of baud rates, the hardware also requires an
> asynchronous external clock input. Clock selection is controlled
> internally by the CCR3 register in the RSCI block.
>
> Due to an incomplete understanding of the hardware, the original binding
> defined only a single clock ("fck"), which is insufficient to describe the
> full capabilities of the RSCI on RZ/T2H. This update corrects the binding
> by allowing up to three clocks and defining the `clock-names` as
> "operation", "bus", and optionally "sck" for the asynchronous clock input.
>
> This is an ABI change, as it modifies the expected number and names of
> clocks. However, since there are no in-kernel consumers of this binding
> yet, the change is considered safe and non-disruptive.
>
> Also remove the unneeded `serial0` alias from the DTS example and use
> the R9A09G077_CLK_PCLKM macro for core clock.
>
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> v12->v13:
> - Rebased on latest linux-next.
> - Updated commit message to clarify the ABI change.
Thanks for the update!
> - Used `R9A09G077_CLK_PCLKM` macro for core clock
Unfortunately include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
is not yet upstream, so you cannot use its definitions yet outside
renesas-clk.
> --- a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> +++ b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> @@ -63,12 +68,8 @@ unevaluatedProperties: false
>
> examples:
> - |
> + #include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> - #include <dt-bindings/clock/renesas-cpg-mssr.h>
> -
> - aliases {
> - serial0 = &sci0;
> - };
>
> sci0: serial@80005000 {
> compatible = "renesas,r9a09g077-rsci";
> @@ -78,7 +79,7 @@ examples:
> <GIC_SPI 592 IRQ_TYPE_EDGE_RISING>,
> <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-names = "eri", "rxi", "txi", "tei";
> - clocks = <&cpg CPG_MOD 108>;
> - clock-names = "fck";
> + clocks = <&cpg CPG_MOD 8>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
> + clock-names = "operation", "bus";
> power-domains = <&cpg>;
> };
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Geert,
On Mon, Jun 30, 2025 at 9:10 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Sat, 28 Jun 2025 at 13:57, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
> >
> > Update the RSCI binding to support an optional secondary clock input on
> > the RZ/T2H SoC. At boot, the RSCI operates using the default synchronous
> > clock (PCLKM core clock), which is enabled by the bootloader. However, to
> > support a wider range of baud rates, the hardware also requires an
> > asynchronous external clock input. Clock selection is controlled
> > internally by the CCR3 register in the RSCI block.
> >
> > Due to an incomplete understanding of the hardware, the original binding
> > defined only a single clock ("fck"), which is insufficient to describe the
> > full capabilities of the RSCI on RZ/T2H. This update corrects the binding
> > by allowing up to three clocks and defining the `clock-names` as
> > "operation", "bus", and optionally "sck" for the asynchronous clock input.
> >
> > This is an ABI change, as it modifies the expected number and names of
> > clocks. However, since there are no in-kernel consumers of this binding
> > yet, the change is considered safe and non-disruptive.
> >
> > Also remove the unneeded `serial0` alias from the DTS example and use
> > the R9A09G077_CLK_PCLKM macro for core clock.
> >
> > Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > ---
> > v12->v13:
> > - Rebased on latest linux-next.
> > - Updated commit message to clarify the ABI change.
>
> Thanks for the update!
>
> > - Used `R9A09G077_CLK_PCLKM` macro for core clock
>
> Unfortunately include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
> is not yet upstream, so you cannot use its definitions yet outside
> renesas-clk.
>
Thanks for pointing that out.
Cheers,
Prabhakar
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