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Sat, 28 Jun 2025 04:57:17 -0700 (PDT) Received: from iku.example.org ([2a06:5906:61b:2d00:dca0:b0f1:f055:ea37]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a88c7e7310sm5247818f8f.18.2025.06.28.04.57.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 28 Jun 2025 04:57:17 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Wolfram Sang , linux-serial@vger.kernel.org, devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v13 1/5] dt-bindings: serial: renesas,rsci: Add optional secondary clock input Date: Sat, 28 Jun 2025 12:57:11 +0100 Message-ID: <20250628115715.102338-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250628115715.102338-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250628115715.102338-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thierry Bultel Update the RSCI binding to support an optional secondary clock input on the RZ/T2H SoC. At boot, the RSCI operates using the default synchronous clock (PCLKM core clock), which is enabled by the bootloader. However, to support a wider range of baud rates, the hardware also requires an asynchronous external clock input. Clock selection is controlled internally by the CCR3 register in the RSCI block. Due to an incomplete understanding of the hardware, the original binding defined only a single clock ("fck"), which is insufficient to describe the full capabilities of the RSCI on RZ/T2H. This update corrects the binding by allowing up to three clocks and defining the `clock-names` as "operation", "bus", and optionally "sck" for the asynchronous clock input. This is an ABI change, as it modifies the expected number and names of clocks. However, since there are no in-kernel consumers of this binding yet, the change is considered safe and non-disruptive. Also remove the unneeded `serial0` alias from the DTS example and use the R9A09G077_CLK_PCLKM macro for core clock. Signed-off-by: Thierry Bultel Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v12->v13: - Rebased on latest linux-next. - Updated commit message to clarify the ABI change. - Used `R9A09G077_CLK_PCLKM` macro for core clock --- .../bindings/serial/renesas,rsci.yaml | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml b/D= ocumentation/devicetree/bindings/serial/renesas,rsci.yaml index 4aacc44bb509..f80cb60ae099 100644 --- a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml @@ -41,10 +41,15 @@ properties: - const: tei =20 clocks: - maxItems: 1 + minItems: 2 + maxItems: 3 =20 clock-names: - const: fck # UART functional clock + minItems: 2 + items: + - const: operation + - const: bus + - const: sck # optional external clock input =20 power-domains: maxItems: 1 @@ -63,12 +68,8 @@ unevaluatedProperties: false =20 examples: - | + #include #include - #include - - aliases { - serial0 =3D &sci0; - }; =20 sci0: serial@80005000 { compatible =3D "renesas,r9a09g077-rsci"; @@ -78,7 +79,7 @@ examples: , ; interrupt-names =3D "eri", "rxi", "txi", "tei"; - clocks =3D <&cpg CPG_MOD 108>; - clock-names =3D "fck"; + clocks =3D <&cpg CPG_MOD 8>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; + clock-names =3D "operation", "bus"; power-domains =3D <&cpg>; }; --=20 2.49.0