gcc_aux_clk is used in PCIe RC and it is not required in pcie phy, in
pcie phy it should be gcc_phy_aux_clk, so remove gcc_aux_clk and
replace it with gcc_phy_aux_clk.
Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 28 +++++++++++++++------------
1 file changed, 16 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index fed34717460f..731bd80fc806 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -7707,16 +7707,18 @@ pcie0_phy: phy@1c04000 {
compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy";
reg = <0x0 0x1c04000 0x0 0x2000>;
- clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+ clocks = <&gcc GCC_PCIE_0_PHY_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_CLKREF_EN>,
<&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
<&gcc GCC_PCIE_0_PIPE_CLK>,
- <&gcc GCC_PCIE_0_PIPEDIV2_CLK>,
- <&gcc GCC_PCIE_0_PHY_AUX_CLK>;
-
- clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe",
- "pipediv2", "phy_aux";
+ <&gcc GCC_PCIE_0_PIPEDIV2_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "rchng",
+ "pipe",
+ "pipediv2";
assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
assigned-clock-rates = <100000000>;
@@ -7873,16 +7875,18 @@ pcie1_phy: phy@1c14000 {
compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy";
reg = <0x0 0x1c14000 0x0 0x4000>;
- clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
+ clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
<&gcc GCC_PCIE_CLKREF_EN>,
<&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
<&gcc GCC_PCIE_1_PIPE_CLK>,
- <&gcc GCC_PCIE_1_PIPEDIV2_CLK>,
- <&gcc GCC_PCIE_1_PHY_AUX_CLK>;
-
- clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe",
- "pipediv2", "phy_aux";
+ <&gcc GCC_PCIE_1_PIPEDIV2_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "rchng",
+ "pipe",
+ "pipediv2";
assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
assigned-clock-rates = <100000000>;
--
2.34.1On 6/25/25 11:00 AM, Ziyue Zhang wrote: > gcc_aux_clk is used in PCIe RC and it is not required in pcie phy, in > pcie phy it should be gcc_phy_aux_clk, so remove gcc_aux_clk and > replace it with gcc_phy_aux_clk. GCC_PCIE_n_PHY_AUX_CLK is a downstream of the PHY's output.. are you sure the PHY should be **consuming** it too? Konrad
On Fri, Jun 27, 2025 at 04:50:57PM +0200, Konrad Dybcio wrote: > On 6/25/25 11:00 AM, Ziyue Zhang wrote: > > gcc_aux_clk is used in PCIe RC and it is not required in pcie phy, in > > pcie phy it should be gcc_phy_aux_clk, so remove gcc_aux_clk and > > replace it with gcc_phy_aux_clk. > > GCC_PCIE_n_PHY_AUX_CLK is a downstream of the PHY's output.. > are you sure the PHY should be **consuming** it too? Could we get a reply here, please? A bunch of Qualcomm SoCs in mainline do exactly this currently even though it may not be correct (and some downstream dts do not use these clocks). Johan
On 7/10/2025 5:43 PM, Johan Hovold wrote: > On Fri, Jun 27, 2025 at 04:50:57PM +0200, Konrad Dybcio wrote: >> On 6/25/25 11:00 AM, Ziyue Zhang wrote: >>> gcc_aux_clk is used in PCIe RC and it is not required in pcie phy, in >>> pcie phy it should be gcc_phy_aux_clk, so remove gcc_aux_clk and >>> replace it with gcc_phy_aux_clk. >> GCC_PCIE_n_PHY_AUX_CLK is a downstream of the PHY's output.. >> are you sure the PHY should be **consuming** it too? > Could we get a reply here, please? > > A bunch of Qualcomm SoCs in mainline do exactly this currently even > though it may not be correct (and some downstream dts do not use these > clocks). > > Johan Hi Johan After reviewing the downstream platforms, it seems that GCC_PCIE_n_PHY_AUX_CLK is generally needed. Would you mind letting us know if there are any platforms where this clock is not required?
On 7/10/25 12:24 PM, Ziyue Zhang wrote: > > On 7/10/2025 5:43 PM, Johan Hovold wrote: >> On Fri, Jun 27, 2025 at 04:50:57PM +0200, Konrad Dybcio wrote: >>> On 6/25/25 11:00 AM, Ziyue Zhang wrote: >>>> gcc_aux_clk is used in PCIe RC and it is not required in pcie phy, in >>>> pcie phy it should be gcc_phy_aux_clk, so remove gcc_aux_clk and >>>> replace it with gcc_phy_aux_clk. >>> GCC_PCIE_n_PHY_AUX_CLK is a downstream of the PHY's output.. >>> are you sure the PHY should be **consuming** it too? >> Could we get a reply here, please? >> >> A bunch of Qualcomm SoCs in mainline do exactly this currently even >> though it may not be correct (and some downstream dts do not use these >> clocks). >> >> Johan > > Hi Johan > > After reviewing the downstream platforms, it seems that GCC_PCIE_n_PHY_AUX_CLK > is generally needed. Would you mind letting us know if there are any platforms > where this clock is not required? Do you base this on "downstream has it", or did you check with the relevant folks internally? I'm still unconvinced by the clock looping back to the PHY. Konrad
On Thu, Jul 10, 2025 at 06:24:57PM +0800, Ziyue Zhang wrote: > > On 7/10/2025 5:43 PM, Johan Hovold wrote: > > On Fri, Jun 27, 2025 at 04:50:57PM +0200, Konrad Dybcio wrote: > >> On 6/25/25 11:00 AM, Ziyue Zhang wrote: > >>> gcc_aux_clk is used in PCIe RC and it is not required in pcie phy, in > >>> pcie phy it should be gcc_phy_aux_clk, so remove gcc_aux_clk and > >>> replace it with gcc_phy_aux_clk. > >> GCC_PCIE_n_PHY_AUX_CLK is a downstream of the PHY's output.. > >> are you sure the PHY should be **consuming** it too? > > Could we get a reply here, please? > > > > A bunch of Qualcomm SoCs in mainline do exactly this currently even > > though it may not be correct (and some downstream dts do not use these > > clocks). > After reviewing the downstream platforms, it seems that GCC_PCIE_n_PHY_AUX_CLK > is generally needed. Would you mind letting us know if there are any platforms > where this clock is not required? Thanks for clarifying. I was think of sc8280xp where the downstream dt did not use this clock (and therefore neither is the dt in mainline currently). Looking again now it seems that clock may not even exist on this platform? Johan
© 2016 - 2025 Red Hat, Inc.