Each PCIe controller on sa8775p includes 'link_down'reset on hardware,
document it.

Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
---
 .../devicetree/bindings/pci/qcom,pcie-sa8775p.yaml  | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml
index 4b91b5608013..510c9e1c28e1 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml
@@ -66,11 +66,14 @@ properties:
       - const: global
 
   resets:
-    maxItems: 1
+    items:
+      - description: PCIe controller reset
+      - description: PCIe link down reset
 
   reset-names:
     items:
-      - const: pci
+      - const: pci # PCIe core reset
+      - const: link_down # PCIe link down reset
 
 required:
   - interconnects
@@ -166,8 +169,10 @@ examples:
 
             power-domains = <&gcc PCIE_0_GDSC>;
 
-            resets = <&gcc GCC_PCIE_0_BCR>;
-            reset-names = "pci";
+            resets = <&gcc GCC_PCIE_0_BCR>,
+                     <&gcc GCC_PCIE_0_LINK_DOWN_BCR>;
+            reset-names = "pci",
+                          "link_down";
 
             perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
             wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
-- 
2.34.1

On Wed, Jun 25, 2025 at 05:00:46PM +0800, Ziyue Zhang wrote:
> Each PCIe controller on sa8775p includes 'link_down'reset on hardware,
> document it.

Please describe what this reset does here as I asked you to earlier.

> Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
> ---
>  .../devicetree/bindings/pci/qcom,pcie-sa8775p.yaml  | 13 +++++++++----
>  1 file changed, 9 insertions(+), 4 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml
> index 4b91b5608013..510c9e1c28e1 100644
> --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml
> @@ -66,11 +66,14 @@ properties:
>        - const: global
>  
>    resets:
> -    maxItems: 1
> +    items:
> +      - description: PCIe controller reset
> +      - description: PCIe link down reset
>  
>    reset-names:
>      items:
> -      - const: pci
> +      - const: pci # PCIe core reset
> +      - const: link_down # PCIe link down reset

I think you can drop the comments since you already describe the resets
above.

Johan

On Wed, Jun 25, 2025 at 05:00:46PM +0800, Ziyue Zhang wrote:
> Each PCIe controller on sa8775p includes 'link_down'reset on hardware,
> document it.

This is an ABI break, so you need to clearly express it and explain the
impact. Following previous Qualcomm feedback we cannot give review to
imperfect commits, because this would be precedent to accept such
imperfectness in the future.

Therefore follow all standard rules about ABI.

Best regards,
Krzysztof

On 6/27/2025 3:08 PM, Krzysztof Kozlowski wrote:
> On Wed, Jun 25, 2025 at 05:00:46PM +0800, Ziyue Zhang wrote:
>> Each PCIe controller on sa8775p includes 'link_down'reset on hardware,
>> document it.
> This is an ABI break, so you need to clearly express it and explain the
> impact. Following previous Qualcomm feedback we cannot give review to
> imperfect commits, because this would be precedent to accept such
> imperfectness in the future.
>
> Therefore follow all standard rules about ABI.
>
> Best regards,
> Krzysztof

Hi Krzysztof


This does not break the ABI. In the Qualcomm PCIe driver, we use the APIs
devm_reset_control_array_get_exclusive, reset_control_assert, and
reset_control_deassert to handle the resets defined in the device tree.
Regardless of how many resets are provided in the DTS, these three APIs
treat them as an array and operate on all of them collectively.
Therefore, adding a new reset does not affect the existing ABI behavior.

BRs
Ziyue

On 11/07/2025 10:26, Ziyue Zhang wrote:
> 
> On 6/27/2025 3:08 PM, Krzysztof Kozlowski wrote:
>> On Wed, Jun 25, 2025 at 05:00:46PM +0800, Ziyue Zhang wrote:
>>> Each PCIe controller on sa8775p includes 'link_down'reset on hardware,
>>> document it.
>> This is an ABI break, so you need to clearly express it and explain the
>> impact. Following previous Qualcomm feedback we cannot give review to
>> imperfect commits, because this would be precedent to accept such
>> imperfectness in the future.
>>
>> Therefore follow all standard rules about ABI.
>>
>> Best regards,
>> Krzysztof
> 
> Hi Krzysztof
> 
> 
> This does not break the ABI. In the Qualcomm PCIe driver, we use the APIs
> devm_reset_control_array_get_exclusive, reset_control_assert, and

I see in the binding requirement of 1 reset before and after your patch:
requirement of two reset lines.

This is an ABI change. My entire comment stays valid, so don't just
deflect it but resolve it.

Best regards,
Krzysztof

On 7/11/25 10:44 AM, Krzysztof Kozlowski wrote:
> On 11/07/2025 10:26, Ziyue Zhang wrote:
>>
>> On 6/27/2025 3:08 PM, Krzysztof Kozlowski wrote:
>>> On Wed, Jun 25, 2025 at 05:00:46PM +0800, Ziyue Zhang wrote:
>>>> Each PCIe controller on sa8775p includes 'link_down'reset on hardware,
>>>> document it.
>>> This is an ABI break, so you need to clearly express it and explain the
>>> impact. Following previous Qualcomm feedback we cannot give review to
>>> imperfect commits, because this would be precedent to accept such
>>> imperfectness in the future.
>>>
>>> Therefore follow all standard rules about ABI.
>>>
>>> Best regards,
>>> Krzysztof
>>
>> Hi Krzysztof
>>
>>
>> This does not break the ABI. In the Qualcomm PCIe driver, we use the APIs
>> devm_reset_control_array_get_exclusive, reset_control_assert, and
> 
> I see in the binding requirement of 1 reset before and after your patch:
> requirement of two reset lines.
> 
> This is an ABI change. My entire comment stays valid, so don't just
> deflect it but resolve it.

Ziyue, the change is good, but it needs a better explanation.

Try something like:

SA8775P PCIe RCs include two reset lines: a core one ("pci") used
to reset most of the block, and a "link_down" one, used to ABCDXYZ.

As the latter was omitted with the initial submisison, describe it.
Because ABCDXYZ is not required for most of the block's functionality,
devicetrees lacking it will not see much of a difference - it is
however required to ensure maximum robustness when shutting down the
core.

----

Note that there are physically more reset lines going to/near the RC,
but many of them are either inaccessible to the OS, or very much
should never ever be. This is the case with most hw blocks, so don't
be surprised if you see a list with more than these two. I believe
"pci" and "link_down" are the only ones intended for OS consumption.

You can see some of that bleeding out to Linux on e.g. some IPQ
platforms that don't have a separate MCU (some flavor of RPM) that
would do the bus management.

Konrad