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charset="utf-8" Each PCIe controller on sa8775p includes 'link_down'reset on hardware, document it. Signed-off-by: Ziyue Zhang --- .../devicetree/bindings/pci/qcom,pcie-sa8775p.yaml | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml b= /Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml index 4b91b5608013..510c9e1c28e1 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml @@ -66,11 +66,14 @@ properties: - const: global =20 resets: - maxItems: 1 + items: + - description: PCIe controller reset + - description: PCIe link down reset =20 reset-names: items: - - const: pci + - const: pci # PCIe core reset + - const: link_down # PCIe link down reset =20 required: - interconnects @@ -166,8 +169,10 @@ examples: =20 power-domains =3D <&gcc PCIE_0_GDSC>; =20 - resets =3D <&gcc GCC_PCIE_0_BCR>; - reset-names =3D "pci"; + resets =3D <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; + reset-names =3D "pci", + "link_down"; =20 perst-gpios =3D <&tlmm 2 GPIO_ACTIVE_LOW>; wake-gpios =3D <&tlmm 0 GPIO_ACTIVE_HIGH>; --=20 2.34.1