Add cpufreq-hw node to support CPU frequency scaling.
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
---
arch/arm64/boot/dts/qcom/qcs615.dtsi | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
index 5adf409d7ce7226042c759cc83ceca331097ae37..d06fc1c157454f635389ff0645fcf4b378270dbc 100644
--- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
@@ -36,6 +36,8 @@ cpu0: cpu@0 {
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&l2_0>;
+ clocks = <&cpufreq_hw 0>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
l2_0: l2-cache {
@@ -56,6 +58,8 @@ cpu1: cpu@100 {
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&l2_100>;
+ clocks = <&cpufreq_hw 0>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
l2_100: l2-cache {
compatible = "cache";
@@ -75,6 +79,8 @@ cpu2: cpu@200 {
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&l2_200>;
+ clocks = <&cpufreq_hw 0>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
l2_200: l2-cache {
compatible = "cache";
@@ -94,6 +100,8 @@ cpu3: cpu@300 {
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&l2_300>;
+ clocks = <&cpufreq_hw 0>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
l2_300: l2-cache {
compatible = "cache";
@@ -113,6 +121,8 @@ cpu4: cpu@400 {
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&l2_400>;
+ clocks = <&cpufreq_hw 0>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
l2_400: l2-cache {
compatible = "cache";
@@ -132,6 +142,8 @@ cpu5: cpu@500 {
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&l2_500>;
+ clocks = <&cpufreq_hw 0>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
l2_500: l2-cache {
compatible = "cache";
@@ -151,6 +163,8 @@ cpu6: cpu@600 {
capacity-dmips-mhz = <1740>;
dynamic-power-coefficient = <404>;
next-level-cache = <&l2_600>;
+ clocks = <&cpufreq_hw 1>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
l2_600: l2-cache {
@@ -171,6 +185,8 @@ cpu7: cpu@700 {
capacity-dmips-mhz = <1740>;
dynamic-power-coefficient = <404>;
next-level-cache = <&l2_700>;
+ clocks = <&cpufreq_hw 1>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
l2_700: l2-cache {
compatible = "cache";
@@ -3891,6 +3907,19 @@ glink_edge: glink-edge {
qcom,remote-pid = <2>;
};
};
+
+ cpufreq_hw: cpufreq@18323000 {
+ compatible = "qcom,sc7180-cpufreq-hw", "qcom,cpufreq-hw";
+ reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
+ reg-names = "freq-domain0", "freq-domain1";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
+ clock-names = "xo", "alternate";
+
+ #freq-domain-cells = <1>;
+ #clock-cells = <1>;
+ };
+
};
arch_timer: timer {
--
2.34.1On Wed, Jun 25, 2025 at 04:44:01PM +0530, Taniya Das wrote:
> Add cpufreq-hw node to support CPU frequency scaling.
>
> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/qcs615.dtsi | 29 +++++++++++++++++++++++++++++
> 1 file changed, 29 insertions(+)
>
> @@ -3891,6 +3907,19 @@ glink_edge: glink-edge {
> qcom,remote-pid = <2>;
> };
> };
> +
> + cpufreq_hw: cpufreq@18323000 {
> + compatible = "qcom,sc7180-cpufreq-hw", "qcom,cpufreq-hw";
Why? Other platforms use a true SoC as the first entry.
> + reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
> + reg-names = "freq-domain0", "freq-domain1";
> +
> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
> + clock-names = "xo", "alternate";
> +
> + #freq-domain-cells = <1>;
> + #clock-cells = <1>;
> + };
> +
> };
>
> arch_timer: timer {
>
> --
> 2.34.1
>
--
With best wishes
Dmitry
On 6/25/2025 5:06 PM, Dmitry Baryshkov wrote:
> On Wed, Jun 25, 2025 at 04:44:01PM +0530, Taniya Das wrote:
>> Add cpufreq-hw node to support CPU frequency scaling.
>>
>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/qcs615.dtsi | 29 +++++++++++++++++++++++++++++
>> 1 file changed, 29 insertions(+)
>>
>> @@ -3891,6 +3907,19 @@ glink_edge: glink-edge {
>> qcom,remote-pid = <2>;
>> };
>> };
>> +
>> + cpufreq_hw: cpufreq@18323000 {
>> + compatible = "qcom,sc7180-cpufreq-hw", "qcom,cpufreq-hw";
>
> Why? Other platforms use a true SoC as the first entry.
>
Dmitry, from cpufreq-hw perspective SC7180 is a exact match for QCS615
and that was the reason to use the same.
>> + reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
>> + reg-names = "freq-domain0", "freq-domain1";
>> +
>> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
>> + clock-names = "xo", "alternate";
>> +
>> + #freq-domain-cells = <1>;
>> + #clock-cells = <1>;
>> + };
>> +
>> };
>>
>> arch_timer: timer {
>>
>> --
>> 2.34.1
>>
>
On 27/06/2025 06:52, Taniya Das wrote:
>
>
> On 6/25/2025 5:06 PM, Dmitry Baryshkov wrote:
>> On Wed, Jun 25, 2025 at 04:44:01PM +0530, Taniya Das wrote:
>>> Add cpufreq-hw node to support CPU frequency scaling.
>>>
>>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>>> ---
>>> arch/arm64/boot/dts/qcom/qcs615.dtsi | 29 +++++++++++++++++++++++++++++
>>> 1 file changed, 29 insertions(+)
>>>
>>> @@ -3891,6 +3907,19 @@ glink_edge: glink-edge {
>>> qcom,remote-pid = <2>;
>>> };
>>> };
>>> +
>>> + cpufreq_hw: cpufreq@18323000 {
>>> + compatible = "qcom,sc7180-cpufreq-hw", "qcom,cpufreq-hw";
>>
>> Why? Other platforms use a true SoC as the first entry.
>>
> Dmitry, from cpufreq-hw perspective SC7180 is a exact match for QCS615
> and that was the reason to use the same.
Please look around. A quick `git grep` would show that every SoC uses
SoC-specific compatible (although some of them are definitely
compatible). The reason is pretty simple: each platform might have
SoC-specific tunings and quirks.
--
With best wishes
Dmitry
On 6/27/2025 6:05 PM, Dmitry Baryshkov wrote:
> On 27/06/2025 06:52, Taniya Das wrote:
>>
>>
>> On 6/25/2025 5:06 PM, Dmitry Baryshkov wrote:
>>> On Wed, Jun 25, 2025 at 04:44:01PM +0530, Taniya Das wrote:
>>>> Add cpufreq-hw node to support CPU frequency scaling.
>>>>
>>>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>>>> ---
>>>> arch/arm64/boot/dts/qcom/qcs615.dtsi | 29 ++++++++++++++++++++++++
>>>> +++++
>>>> 1 file changed, 29 insertions(+)
>>>>
>>>> @@ -3891,6 +3907,19 @@ glink_edge: glink-edge {
>>>> qcom,remote-pid = <2>;
>>>> };
>>>> };
>>>> +
>>>> + cpufreq_hw: cpufreq@18323000 {
>>>> + compatible = "qcom,sc7180-cpufreq-hw", "qcom,cpufreq-hw";
>>>
>>> Why? Other platforms use a true SoC as the first entry.
>>>
>> Dmitry, from cpufreq-hw perspective SC7180 is a exact match for QCS615
>> and that was the reason to use the same.
>
> Please look around. A quick `git grep` would show that every SoC uses
> SoC-specific compatible (although some of them are definitely
> compatible). The reason is pretty simple: each platform might have SoC-
> specific tunings and quirks.
>
Sure Dmitry, I will update to use "qcom,qcs615-cpufreq-hw"
On 6/27/25 5:52 AM, Taniya Das wrote:
>
>
> On 6/25/2025 5:06 PM, Dmitry Baryshkov wrote:
>> On Wed, Jun 25, 2025 at 04:44:01PM +0530, Taniya Das wrote:
>>> Add cpufreq-hw node to support CPU frequency scaling.
>>>
>>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>>> ---
>>> arch/arm64/boot/dts/qcom/qcs615.dtsi | 29 +++++++++++++++++++++++++++++
>>> 1 file changed, 29 insertions(+)
>>>
>>> @@ -3891,6 +3907,19 @@ glink_edge: glink-edge {
>>> qcom,remote-pid = <2>;
>>> };
>>> };
>>> +
>>> + cpufreq_hw: cpufreq@18323000 {
>>> + compatible = "qcom,sc7180-cpufreq-hw", "qcom,cpufreq-hw";
>>
>> Why? Other platforms use a true SoC as the first entry.
>>
> Dmitry, from cpufreq-hw perspective SC7180 is a exact match for QCS615
> and that was the reason to use the same.
The only compatible consumed by the driver is the last one in this case,
meaning sc7180 is only there so that if we discover quirks very specific
to sc7180 down the line, we can add some exceptions in code
Reusing sc7180 would remove the ability to address any quirks that would
concern qcs615 specifically, which can happen due to hw design, fw
quirks etc.
Konrad
On 6/27/2025 5:37 PM, Konrad Dybcio wrote:
> On 6/27/25 5:52 AM, Taniya Das wrote:
>>
>>
>> On 6/25/2025 5:06 PM, Dmitry Baryshkov wrote:
>>> On Wed, Jun 25, 2025 at 04:44:01PM +0530, Taniya Das wrote:
>>>> Add cpufreq-hw node to support CPU frequency scaling.
>>>>
>>>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>>>> ---
>>>> arch/arm64/boot/dts/qcom/qcs615.dtsi | 29 +++++++++++++++++++++++++++++
>>>> 1 file changed, 29 insertions(+)
>>>>
>>>> @@ -3891,6 +3907,19 @@ glink_edge: glink-edge {
>>>> qcom,remote-pid = <2>;
>>>> };
>>>> };
>>>> +
>>>> + cpufreq_hw: cpufreq@18323000 {
>>>> + compatible = "qcom,sc7180-cpufreq-hw", "qcom,cpufreq-hw";
>>>
>>> Why? Other platforms use a true SoC as the first entry.
>>>
>> Dmitry, from cpufreq-hw perspective SC7180 is a exact match for QCS615
>> and that was the reason to use the same.
>
> The only compatible consumed by the driver is the last one in this case,
> meaning sc7180 is only there so that if we discover quirks very specific
> to sc7180 down the line, we can add some exceptions in code
>
> Reusing sc7180 would remove the ability to address any quirks that would
> concern qcs615 specifically, which can happen due to hw design, fw
> quirks etc.
>
There are no quirks for QCS615 as the block is a re-use in design. I
will add the new update to use the "qcom,qcs615-cpufreq-hw".
> Konrad
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