.../bindings/arm/qcom,coresight-ctcu.yaml | 9 +- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 153 ++++++++++++++++++ 2 files changed, 160 insertions(+), 2 deletions(-)
Enable CTCU device for QCS8300 platform. Add a fallback mechnasim in binding to utilize the compitable of the SA8775p platform becuase the CTCU for QCS8300 shares same configurations as SA8775p platform. Changes in V2: 1. Add Krzysztof's R-B tag for dt-binding patch. 2. Add Konrad's Acked-by tag for dt patch. 3. Rebased on tag next-20250623. 4. Missed email addresses for coresight's maintainers in V1, loop them. Link to V1 - https://lore.kernel.org/all/20250327024943.3502313-1-jie.gan@oss.qualcomm.com/ Jie Gan (2): dt-bindings: arm: add CTCU device for QCS8300 arm64: dts: qcom: qcs8300: Add CTCU and ETR nodes .../bindings/arm/qcom,coresight-ctcu.yaml | 9 +- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 153 ++++++++++++++++++ 2 files changed, 160 insertions(+), 2 deletions(-) -- 2.34.1
On 6/24/2025 5:59 PM, Jie Gan wrote: > Enable CTCU device for QCS8300 platform. Add a fallback mechnasim in binding to utilize > the compitable of the SA8775p platform becuase the CTCU for QCS8300 shares same > configurations as SA8775p platform. Gentle ping. Hi Suzuki, Mike, James, Rob Can you plz help to review the patch from Coresight view? Thanks, Jie > > Changes in V2: > 1. Add Krzysztof's R-B tag for dt-binding patch. > 2. Add Konrad's Acked-by tag for dt patch. > 3. Rebased on tag next-20250623. > 4. Missed email addresses for coresight's maintainers in V1, loop them. > Link to V1 - https://lore.kernel.org/all/20250327024943.3502313-1-jie.gan@oss.qualcomm.com/ > > Jie Gan (2): > dt-bindings: arm: add CTCU device for QCS8300 > arm64: dts: qcom: qcs8300: Add CTCU and ETR nodes > > .../bindings/arm/qcom,coresight-ctcu.yaml | 9 +- > arch/arm64/boot/dts/qcom/qcs8300.dtsi | 153 ++++++++++++++++++ > 2 files changed, 160 insertions(+), 2 deletions(-) >
On 7/15/2025 8:41 AM, Jie Gan wrote: > > > On 6/24/2025 5:59 PM, Jie Gan wrote: >> Enable CTCU device for QCS8300 platform. Add a fallback mechnasim in >> binding to utilize >> the compitable of the SA8775p platform becuase the CTCU for QCS8300 >> shares same >> configurations as SA8775p platform. > > Gentle ping. Gentle ping. Thanks, Jie > > Hi Suzuki, Mike, James, Rob > > Can you plz help to review the patch from Coresight view? > > Thanks, > Jie > >> >> Changes in V2: >> 1. Add Krzysztof's R-B tag for dt-binding patch. >> 2. Add Konrad's Acked-by tag for dt patch. >> 3. Rebased on tag next-20250623. >> 4. Missed email addresses for coresight's maintainers in V1, loop them. >> Link to V1 - https://lore.kernel.org/all/20250327024943.3502313-1- >> jie.gan@oss.qualcomm.com/ >> >> Jie Gan (2): >> dt-bindings: arm: add CTCU device for QCS8300 >> arm64: dts: qcom: qcs8300: Add CTCU and ETR nodes >> >> .../bindings/arm/qcom,coresight-ctcu.yaml | 9 +- >> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 153 ++++++++++++++++++ >> 2 files changed, 160 insertions(+), 2 deletions(-) >> > >
On 7/28/2025 9:08 AM, Jie Gan wrote: > > > On 7/15/2025 8:41 AM, Jie Gan wrote: >> >> >> On 6/24/2025 5:59 PM, Jie Gan wrote: >>> Enable CTCU device for QCS8300 platform. Add a fallback mechnasim in >>> binding to utilize >>> the compitable of the SA8775p platform becuase the CTCU for QCS8300 >>> shares same >>> configurations as SA8775p platform. >> >> Gentle ping. > > Gentle ping. Gentle ping. Hi Coresight maintainers, Can you please help to review the patch? Thanks, Jie > > Thanks, > Jie > >> >> Hi Suzuki, Mike, James, Rob >> >> Can you plz help to review the patch from Coresight view? >> >> Thanks, >> Jie >> >>> >>> Changes in V2: >>> 1. Add Krzysztof's R-B tag for dt-binding patch. >>> 2. Add Konrad's Acked-by tag for dt patch. >>> 3. Rebased on tag next-20250623. >>> 4. Missed email addresses for coresight's maintainers in V1, loop them. >>> Link to V1 - https://lore.kernel.org/all/20250327024943.3502313-1- >>> jie.gan@oss.qualcomm.com/ >>> >>> Jie Gan (2): >>> dt-bindings: arm: add CTCU device for QCS8300 >>> arm64: dts: qcom: qcs8300: Add CTCU and ETR nodes >>> >>> .../bindings/arm/qcom,coresight-ctcu.yaml | 9 +- >>> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 153 ++++++++++++++++++ >>> 2 files changed, 160 insertions(+), 2 deletions(-) >>> >> >> >
Hi Jie, On Tue, 5 Aug 2025 at 05:11, Jie Gan <jie.gan@oss.qualcomm.com> wrote: > > > > On 7/28/2025 9:08 AM, Jie Gan wrote: > > > > > > On 7/15/2025 8:41 AM, Jie Gan wrote: > >> > >> > >> On 6/24/2025 5:59 PM, Jie Gan wrote: > >>> Enable CTCU device for QCS8300 platform. Add a fallback mechnasim in > >>> binding to utilize > >>> the compitable of the SA8775p platform becuase the CTCU for QCS8300 > >>> shares same > >>> configurations as SA8775p platform. > >> > >> Gentle ping. > > > > Gentle ping. > > Gentle ping. > Hi Coresight maintainers, > > Can you please help to review the patch? > > Thanks, > Jie > > > > > Thanks, > > Jie > > > >> > >> Hi Suzuki, Mike, James, Rob > >> > >> Can you plz help to review the patch from Coresight view? > >> > >> Thanks, > >> Jie > >> > >>> > >>> Changes in V2: > >>> 1. Add Krzysztof's R-B tag for dt-binding patch. > >>> 2. Add Konrad's Acked-by tag for dt patch. > >>> 3. Rebased on tag next-20250623. > >>> 4. Missed email addresses for coresight's maintainers in V1, loop them. > >>> Link to V1 - https://lore.kernel.org/all/20250327024943.3502313-1- > >>> jie.gan@oss.qualcomm.com/ > >>> > >>> Jie Gan (2): > >>> dt-bindings: arm: add CTCU device for QCS8300 > >>> arm64: dts: qcom: qcs8300: Add CTCU and ETR nodes > >>> > >>> .../bindings/arm/qcom,coresight-ctcu.yaml | 9 +- > >>> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 153 ++++++++++++++++++ > >>> 2 files changed, 160 insertions(+), 2 deletions(-) > >>> > >> > >> > > > You need to send a new patch addressing the comments made by Krzysztof.. Regards Mike -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK
On 8/5/2025 5:53 PM, Mike Leach wrote: > Hi Jie, > > On Tue, 5 Aug 2025 at 05:11, Jie Gan <jie.gan@oss.qualcomm.com> wrote: >> >> >> >> On 7/28/2025 9:08 AM, Jie Gan wrote: >>> >>> >>> On 7/15/2025 8:41 AM, Jie Gan wrote: >>>> >>>> >>>> On 6/24/2025 5:59 PM, Jie Gan wrote: >>>>> Enable CTCU device for QCS8300 platform. Add a fallback mechnasim in >>>>> binding to utilize >>>>> the compitable of the SA8775p platform becuase the CTCU for QCS8300 >>>>> shares same >>>>> configurations as SA8775p platform. >>>> >>>> Gentle ping. >>> >>> Gentle ping. >> >> Gentle ping. >> Hi Coresight maintainers, >> >> Can you please help to review the patch? >> >> Thanks, >> Jie >> >>> >>> Thanks, >>> Jie >>> >>>> >>>> Hi Suzuki, Mike, James, Rob >>>> >>>> Can you plz help to review the patch from Coresight view? >>>> >>>> Thanks, >>>> Jie >>>> >>>>> >>>>> Changes in V2: >>>>> 1. Add Krzysztof's R-B tag for dt-binding patch. >>>>> 2. Add Konrad's Acked-by tag for dt patch. >>>>> 3. Rebased on tag next-20250623. >>>>> 4. Missed email addresses for coresight's maintainers in V1, loop them. >>>>> Link to V1 - https://lore.kernel.org/all/20250327024943.3502313-1- >>>>> jie.gan@oss.qualcomm.com/ >>>>> >>>>> Jie Gan (2): >>>>> dt-bindings: arm: add CTCU device for QCS8300 >>>>> arm64: dts: qcom: qcs8300: Add CTCU and ETR nodes >>>>> >>>>> .../bindings/arm/qcom,coresight-ctcu.yaml | 9 +- >>>>> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 153 ++++++++++++++++++ >>>>> 2 files changed, 160 insertions(+), 2 deletions(-) >>>>> >>>> >>>> >>> >> > > You need to send a new patch addressing the comments made by Krzysztof.. Hi Mike, I just proposed an idea to add a common compatible for CTCU device, its not about the patch series itself. We dropped the idea and prefer to add the board specific compatible for each platform. Thanks, Jie > > Regards > > Mike
On 8/5/2025 6:25 PM, Jie Gan wrote: > > > On 8/5/2025 5:53 PM, Mike Leach wrote: >> Hi Jie, >> >> On Tue, 5 Aug 2025 at 05:11, Jie Gan <jie.gan@oss.qualcomm.com> wrote: >>> >>> >>> >>> On 7/28/2025 9:08 AM, Jie Gan wrote: >>>> >>>> >>>> On 7/15/2025 8:41 AM, Jie Gan wrote: >>>>> >>>>> >>>>> On 6/24/2025 5:59 PM, Jie Gan wrote: >>>>>> Enable CTCU device for QCS8300 platform. Add a fallback mechnasim in >>>>>> binding to utilize >>>>>> the compitable of the SA8775p platform becuase the CTCU for QCS8300 >>>>>> shares same >>>>>> configurations as SA8775p platform. >>>>> >>>>> Gentle ping. >>>> >>>> Gentle ping. >>> >>> Gentle ping. >>> Hi Coresight maintainers, >>> >>> Can you please help to review the patch? >>> >>> Thanks, >>> Jie >>> >>>> >>>> Thanks, >>>> Jie >>>> >>>>> >>>>> Hi Suzuki, Mike, James, Rob >>>>> >>>>> Can you plz help to review the patch from Coresight view? >>>>> >>>>> Thanks, >>>>> Jie >>>>> >>>>>> >>>>>> Changes in V2: >>>>>> 1. Add Krzysztof's R-B tag for dt-binding patch. >>>>>> 2. Add Konrad's Acked-by tag for dt patch. >>>>>> 3. Rebased on tag next-20250623. >>>>>> 4. Missed email addresses for coresight's maintainers in V1, loop >>>>>> them. >>>>>> Link to V1 - https://lore.kernel.org/all/20250327024943.3502313-1- >>>>>> jie.gan@oss.qualcomm.com/ >>>>>> >>>>>> Jie Gan (2): >>>>>> dt-bindings: arm: add CTCU device for QCS8300 >>>>>> arm64: dts: qcom: qcs8300: Add CTCU and ETR nodes >>>>>> >>>>>> .../bindings/arm/qcom,coresight-ctcu.yaml | 9 +- >>>>>> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 153 +++++++++++ >>>>>> +++++++ >>>>>> 2 files changed, 160 insertions(+), 2 deletions(-) >>>>>> >>>>> >>>>> >>>> >>> >> >> You need to send a new patch addressing the comments made by Krzysztof.. > > Hi Mike, > > I just proposed an idea to add a common compatible for CTCU device, its > not about the patch series itself. We dropped the idea and prefer to add > the board specific compatible for each platform. > > Thanks, > Jie Hi Suzuki, Mike, James We already have the tag from dt-binding and dt maintainers. We haven't additional modification for this patch series. Can you please help to review the patch series from Coresight View? Thanks, Jie > >> >> Regards >> >> Mike > >
On 6/24/2025 5:59 PM, Jie Gan wrote:
> Enable CTCU device for QCS8300 platform. Add a fallback mechnasim in binding to utilize
> the compitable of the SA8775p platform becuase the CTCU for QCS8300 shares same
> configurations as SA8775p platform.
Hi dear maintainers,
I just realized it would be more efficient to introduce a common
compatible string for SoCs that include two TMC ETR devices.
Most of these SoCs share the same CTCU data configuration, such as the
offsets for the ATID and IRQ registers, because they integrate the same
version of the CTCU hardware.
So I propose introducing a common compatible string,
"coresight-ctcu-v2", to simplify the device tree configuration for these
platforms.
Here is the new dt-binding format:
properties:
compatible:
oneOf:
- items:
- enum:
- qcom,sa8775p-ctcu
- qcom,qcs8300-ctcu
- const: qcom,coresight-ctcu-v2
- enum:
- qcom,coresight-ctcu-v2
Thanks,
Jie
>
> Changes in V2:
> 1. Add Krzysztof's R-B tag for dt-binding patch.
> 2. Add Konrad's Acked-by tag for dt patch.
> 3. Rebased on tag next-20250623.
> 4. Missed email addresses for coresight's maintainers in V1, loop them.
> Link to V1 - https://lore.kernel.org/all/20250327024943.3502313-1-jie.gan@oss.qualcomm.com/
>
> Jie Gan (2):
> dt-bindings: arm: add CTCU device for QCS8300
> arm64: dts: qcom: qcs8300: Add CTCU and ETR nodes
>
> .../bindings/arm/qcom,coresight-ctcu.yaml | 9 +-
> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 153 ++++++++++++++++++
> 2 files changed, 160 insertions(+), 2 deletions(-)
>
On 25/06/2025 02:59, Jie Gan wrote: > > > On 6/24/2025 5:59 PM, Jie Gan wrote: >> Enable CTCU device for QCS8300 platform. Add a fallback mechnasim in binding to utilize >> the compitable of the SA8775p platform becuase the CTCU for QCS8300 shares same >> configurations as SA8775p platform. > > Hi dear maintainers, > > I just realized it would be more efficient to introduce a common > compatible string for SoCs that include two TMC ETR devices. > > Most of these SoCs share the same CTCU data configuration, such as the "Most" basically disqualifies your idea. > offsets for the ATID and IRQ registers, because they integrate the same > version of the CTCU hardware. > > So I propose introducing a common compatible string, > "coresight-ctcu-v2", to simplify the device tree configuration for these > platforms. This is explained in writing bindings. Best regards, Krzysztof
On 7/4/2025 3:54 PM, Krzysztof Kozlowski wrote: > On 25/06/2025 02:59, Jie Gan wrote: >> >> >> On 6/24/2025 5:59 PM, Jie Gan wrote: >>> Enable CTCU device for QCS8300 platform. Add a fallback mechnasim in binding to utilize >>> the compitable of the SA8775p platform becuase the CTCU for QCS8300 shares same >>> configurations as SA8775p platform. >> >> Hi dear maintainers, >> >> I just realized it would be more efficient to introduce a common >> compatible string for SoCs that include two TMC ETR devices. >> >> Most of these SoCs share the same CTCU data configuration, such as the > > "Most" basically disqualifies your idea. Okay, it's not a proper expression. SoCs included two ETR devices shared same configuration. So I think use a common compatible for these SoCs is make sense for me and dont need to update the dt-binding again and again... I will send a new patch to address this idea if it's acceptable. > >> offsets for the ATID and IRQ registers, because they integrate the same >> version of the CTCU hardware. >> >> So I propose introducing a common compatible string, >> "coresight-ctcu-v2", to simplify the device tree configuration for these >> platforms. > > This is explained in writing bindings. Yeah, explained in the code lines.. Thanks, Jie > > Best regards, > Krzysztof
On 04/07/2025 10:07, Jie Gan wrote: > >> >>> offsets for the ATID and IRQ registers, because they integrate the same >>> version of the CTCU hardware. >>> >>> So I propose introducing a common compatible string, >>> "coresight-ctcu-v2", to simplify the device tree configuration for these >>> platforms. >> >> This is explained in writing bindings. > > Yeah, explained in the code lines.. I meant explained in writing bindings document. Please read writing bindings first. Best regards, Krzysztof
On 7/4/2025 4:10 PM, Krzysztof Kozlowski wrote: > On 04/07/2025 10:07, Jie Gan wrote: >> >>> >>>> offsets for the ATID and IRQ registers, because they integrate the same >>>> version of the CTCU hardware. >>>> >>>> So I propose introducing a common compatible string, >>>> "coresight-ctcu-v2", to simplify the device tree configuration for these >>>> platforms. >>> >>> This is explained in writing bindings. >> >> Yeah, explained in the code lines.. > I meant explained in writing bindings document. Please read writing > bindings first. OK, will check, sorry for the misunderstanding. Thanks, Jie > > Best regards, > Krzysztof
On 7/4/2025 4:14 PM, Jie Gan wrote: > > > On 7/4/2025 4:10 PM, Krzysztof Kozlowski wrote: >> On 04/07/2025 10:07, Jie Gan wrote: >>> >>>> >>>>> offsets for the ATID and IRQ registers, because they integrate the >>>>> same >>>>> version of the CTCU hardware. >>>>> >>>>> So I propose introducing a common compatible string, >>>>> "coresight-ctcu-v2", to simplify the device tree configuration for >>>>> these >>>>> platforms. >>>> >>>> This is explained in writing bindings. >>> >>> Yeah, explained in the code lines.. >> I meant explained in writing bindings document. Please read writing >> bindings first. > > OK, will check, sorry for the misunderstanding. Hi Krzysztof I checked previous comments and document. Can you plz help to confirm that we prefer a board specific compatible instead of a generic compatible, am right? Thanks, Jie > > Thanks, > Jie > >> >> Best regards, >> Krzysztof > >
On 6/25/2025 8:59 AM, Jie Gan wrote: > > > On 6/24/2025 5:59 PM, Jie Gan wrote: >> Enable CTCU device for QCS8300 platform. Add a fallback mechnasim in >> binding to utilize >> the compitable of the SA8775p platform becuase the CTCU for QCS8300 >> shares same >> configurations as SA8775p platform. > > Hi dear maintainers, > > I just realized it would be more efficient to introduce a common > compatible string for SoCs that include two TMC ETR devices. > > Most of these SoCs share the same CTCU data configuration, such as the > offsets for the ATID and IRQ registers, because they integrate the same > version of the CTCU hardware. > > So I propose introducing a common compatible string, "coresight-ctcu- > v2", to simplify the device tree configuration for these platforms. > > Here is the new dt-binding format: > > properties: > compatible: > oneOf: > - items: > - enum: > - qcom,sa8775p-ctcu > - qcom,qcs8300-ctcu > - const: qcom,coresight-ctcu-v2 > - enum: > - qcom,coresight-ctcu-v2 > > Thanks, > Jie Gentle ping. Thanks, Jie > >> >> Changes in V2: >> 1. Add Krzysztof's R-B tag for dt-binding patch. >> 2. Add Konrad's Acked-by tag for dt patch. >> 3. Rebased on tag next-20250623. >> 4. Missed email addresses for coresight's maintainers in V1, loop them. >> Link to V1 - https://lore.kernel.org/all/20250327024943.3502313-1- >> jie.gan@oss.qualcomm.com/ >> >> Jie Gan (2): >> dt-bindings: arm: add CTCU device for QCS8300 >> arm64: dts: qcom: qcs8300: Add CTCU and ETR nodes >> >> .../bindings/arm/qcom,coresight-ctcu.yaml | 9 +- >> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 153 ++++++++++++++++++ >> 2 files changed, 160 insertions(+), 2 deletions(-) >> > >
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