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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-749b5e08ccfsm1456443b3a.6.2025.06.24.02.59.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Jun 2025 02:59:15 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jie.gan@oss.qualcomm.com, Krzysztof Kozlowski Subject: [PATCH v2 1/2] dt-bindings: arm: add CTCU device for QCS8300 Date: Tue, 24 Jun 2025 17:59:04 +0800 Message-Id: <20250624095905.7609-2-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250624095905.7609-1-jie.gan@oss.qualcomm.com> References: <20250624095905.7609-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: p0AB_B9AY49upPIedYHPi59GNZhw0wUY X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjI0MDA4NCBTYWx0ZWRfXzM8ivIrNVZfj 8CF+IH1jpRYnCEw7DOl/BaUrBe7z7jITPCsqT9g2UeB5zA6qIy2N77tzYSsG+dM5wVfut13aVes 7ZhlAIXejtRouN0MBVIVfPBnwvhIx5az4au+r75NtFO7Fc981nULp/RFlXDDyv5DXZ8ZvmQV2S4 ppDGwu32IKkbkRHucouPaVWqtM0ejqCEaYpF000JuVCbj+Z4PpkvtMQHbp43qvU2CTIuRiO60g/ m4yR2flgdQhVFi2Rj2Fd8oMCa6Mfrzg5OVl+r0g0SKTRxBR1+kxOf6hVj34YZUpjBMrLiCNuxsk 5T3rgf9k9tXL4OrVFAFQ0ZT5P1OweF0feMsVq7Y4JZu55LIGuWn33Iqe/xsYpE4iq4/oAHPXNGm rLF6g/fxjshuG73hfb+AnuZD/ABtU0/zK5tVKGJaUO+DId33Uy6v7Se8CCEvQRIZWl+fIo0A X-Authority-Analysis: v=2.4 cv=L4kdQ/T8 c=1 sm=1 tr=0 ts=685a76f5 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=6IFa9wvqVegA:10 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=T1NhNMajUKWQjJ4YovQA:9 a=IoOABgeZipijB_acs4fv:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: p0AB_B9AY49upPIedYHPi59GNZhw0wUY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-06-24_03,2025-06-23_07,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 malwarescore=0 bulkscore=0 clxscore=1015 suspectscore=0 adultscore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 spamscore=0 phishscore=0 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506240084 Content-Type: text/plain; charset="utf-8" The CTCU device for QCS8300 shares the same configurations as SA8775p. Add a fallback to enable the CTCU for QCS8300 to utilize the compitable of the SA8775p. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Jie Gan --- .../devicetree/bindings/arm/qcom,coresight-ctcu.yaml | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml= b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml index 843b52eaf872..7f3aa503da53 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml @@ -26,8 +26,13 @@ description: | =20 properties: compatible: - enum: - - qcom,sa8775p-ctcu + oneOf: + - items: + - enum: + - qcom,qcs8300-ctcu + - const: qcom,sa8775p-ctcu + - enum: + - qcom,sa8775p-ctcu =20 reg: maxItems: 1 --=20 2.34.1 From nobody Wed Oct 8 21:41:33 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 415B6281376 for ; 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-749b5e08ccfsm1456443b3a.6.2025.06.24.02.59.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Jun 2025 02:59:20 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jie.gan@oss.qualcomm.com, Konrad Dybcio Subject: [PATCH v2 2/2] arm64: dts: qcom: qcs8300: Add CTCU and ETR nodes Date: Tue, 24 Jun 2025 17:59:05 +0800 Message-Id: <20250624095905.7609-3-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250624095905.7609-1-jie.gan@oss.qualcomm.com> References: <20250624095905.7609-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: FtIocaI1px09ksaHDWTL7B187q3F6TfT X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjI0MDA4NCBTYWx0ZWRfXz4I6TJOcjDQf SQpOpzajJwpFgh7cAUcSxoxeLv3X3tH7ZYksjGDTgCrqHDAyo2tVuy/+jxA2gfvevzyfowM4E5l hsLZQXpwa2zA8IQlf1kjuUqil7zgoFu2NG91kpp4anOzlCVLqCBw+bTDQ7qYFHroBrIQynKiiRG lfryw6iiYTw31uq4vJopQbs8ElbwMeJs0i9up6bbc/0P5/R8kJVg+VBnC0q225bm02i+9SiNgBW l/9Me/pQ+s/+Hb/Q9iBLn3IjVtLPUsc5/Z0KCoYOjEq75dzBE8Qor0t7MEki5hnvweA92yhyb98 udHwVhgME8YEy+CoEh5doiiA6RhvteHKiRdjljrY9xcyZW7MwHBNdmyGJPRbU5lcMWE5WD1nP2C vpRfGr8OAM3F7d+OrcDZrhyGyXyMEYMGISEnsu1AmOQudDzSrE4+vF0kRiyhkx8XNPULOAON X-Authority-Analysis: v=2.4 cv=L4kdQ/T8 c=1 sm=1 tr=0 ts=685a76fa cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=6IFa9wvqVegA:10 a=EUspDBNiAAAA:8 a=xJyy5nzPNu-aANFJA0oA:9 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-GUID: FtIocaI1px09ksaHDWTL7B187q3F6TfT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-06-24_03,2025-06-23_07,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 malwarescore=0 bulkscore=0 clxscore=1015 suspectscore=0 adultscore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 spamscore=0 phishscore=0 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506240084 Content-Type: text/plain; charset="utf-8" Add CTCU and ETR nodes in DT to enable expected functionalities. Acked-by: Konrad Dybcio Signed-off-by: Jie Gan --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 153 ++++++++++++++++++++++++++ 1 file changed, 153 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qc= om/qcs8300.dtsi index 7ada029c32c1..7c235dc7cbdd 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -2154,6 +2154,35 @@ lpass_ag_noc: interconnect@3c40000 { qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 + ctcu@4001000 { + compatible =3D "qcom,qcs8300-ctcu", "qcom,sa8775p-ctcu"; + reg =3D <0x0 0x04001000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb"; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + ctcu_in0: endpoint { + remote-endpoint =3D <&etr0_out>; + }; + }; + + port@1 { + reg =3D <1>; + + ctcu_in1: endpoint { + remote-endpoint =3D <&etr1_out>; + }; + }; + }; + }; + stm@4002000 { compatible =3D "arm,coresight-stm", "arm,primecell"; reg =3D <0x0 0x04002000 0x0 0x1000>, @@ -2348,6 +2377,122 @@ qdss_funnel_out: endpoint { }; }; =20 + replicator@4046000 { + compatible =3D "arm,coresight-dynamic-replicator", "arm,primecell"; + reg =3D <0x0 0x04046000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + port { + qdss_rep_in: endpoint { + remote-endpoint =3D <&swao_rep_out0>; + }; + }; + }; + + out-ports { + port { + qdss_rep_out0: endpoint { + remote-endpoint =3D <&etr_rep_in>; + }; + }; + }; + }; + + tmc@4048000 { + compatible =3D "arm,coresight-tmc", "arm,primecell"; + reg =3D <0x0 0x04048000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + iommus =3D <&apps_smmu 0x04c0 0x00>; + + arm,scatter-gather; + + in-ports { + port { + etr0_in: endpoint { + remote-endpoint =3D <&etr_rep_out0>; + }; + }; + }; + + out-ports { + port { + etr0_out: endpoint { + remote-endpoint =3D <&ctcu_in0>; + }; + }; + }; + }; + + replicator@404e000 { + compatible =3D "arm,coresight-dynamic-replicator", "arm,primecell"; + reg =3D <0x0 0x0404e000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + port { + etr_rep_in: endpoint { + remote-endpoint =3D <&qdss_rep_out0>; + }; + }; + }; + + out-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + etr_rep_out0: endpoint { + remote-endpoint =3D <&etr0_in>; + }; + }; + + port@1 { + reg =3D <1>; + + etr_rep_out1: endpoint { + remote-endpoint =3D <&etr1_in>; + }; + }; + }; + }; + + tmc@404f000 { + compatible =3D "arm,coresight-tmc", "arm,primecell"; + reg =3D <0x0 0x0404f000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + iommus =3D <&apps_smmu 0x04a0 0x40>; + + arm,scatter-gather; + arm,buffer-size =3D <0x400000>; + + in-ports { + port { + etr1_in: endpoint { + remote-endpoint =3D <&etr_rep_out1>; + }; + }; + }; + + out-ports { + port { + etr1_out: endpoint { + remote-endpoint =3D <&ctcu_in1>; + }; + }; + }; + }; + tpdm@4841000 { compatible =3D "qcom,coresight-tpdm", "arm,primecell"; reg =3D <0x0 0x04841000 0x0 0x1000>; @@ -2777,6 +2922,14 @@ out-ports { #address-cells =3D <1>; #size-cells =3D <0>; =20 + port@0 { + reg =3D <0>; + + swao_rep_out0: endpoint { + remote-endpoint =3D <&qdss_rep_in>; + }; + }; + port@1 { reg =3D <1>; =20 --=20 2.34.1