Add initial device tree support for the AX3000 SoC and its evaluation
platform. The AX3000 is a multi-core SoC featuring 4 Cortex-A53 cores,
Secure Vault, AI Engine and Firewall.

This commit adds support for Cortex-A53 CPUs, timer, UARTs, and I3C
controllers on the AX3000 evaluation board.

Signed-off-by: Harshit Shah <hshah@axiado.com>
---
 arch/arm64/boot/dts/Makefile              |   1 +
 arch/arm64/boot/dts/axiado/Makefile       |   2 +
 arch/arm64/boot/dts/axiado/ax3000-evk.dts |  79 +++++
 arch/arm64/boot/dts/axiado/ax3000.dtsi    | 488 ++++++++++++++++++++++++++++++
 4 files changed, 570 insertions(+)

diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 79b73a21ddc22b17308554e502f8207392935b45..47dd8a1a7960d179ee28969a1d6750bfa0d73da1 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -9,6 +9,7 @@ subdir-y += amlogic
 subdir-y += apm
 subdir-y += apple
 subdir-y += arm
+subdir-y += axiado
 subdir-y += bitmain
 subdir-y += blaize
 subdir-y += broadcom
diff --git a/arch/arm64/boot/dts/axiado/Makefile b/arch/arm64/boot/dts/axiado/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..6676ad07db6129f8b333b0feffee705d272517c2
--- /dev/null
+++ b/arch/arm64/boot/dts/axiado/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_AXIADO) += ax3000-evk.dtb
diff --git a/arch/arm64/boot/dts/axiado/ax3000-evk.dts b/arch/arm64/boot/dts/axiado/ax3000-evk.dts
new file mode 100644
index 0000000000000000000000000000000000000000..cc3bcf681c32430d251f20f6d52905423c182f3b
--- /dev/null
+++ b/arch/arm64/boot/dts/axiado/ax3000-evk.dts
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021-25 Axiado Corporation (or its affiliates). All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "ax3000.dtsi"
+
+/ {
+	model = "Axiado AX3000 EVK";
+	compatible = "axiado,ax3000-evk", "axiado,ax3000";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	aliases {
+		serial3 = &uart3;
+	};
+
+	chosen {
+		stdout-path = "serial3:115200";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		/* Cortex-A53 will use following memory map */
+		reg = <0x00000000 0x3D000000 0x00000000 0x23000000>,
+		      <0x00000004 0x00000000 0x00000000 0x80000000>;
+	};
+};
+
+/* GPIO bank 0 - 7 */
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpio3 {
+	status = "okay";
+};
+
+&gpio4 {
+	status = "okay";
+};
+
+&gpio5 {
+	status = "okay";
+};
+
+&gpio6 {
+	status = "okay";
+};
+
+&gpio7 {
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&uart3 {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/axiado/ax3000.dtsi b/arch/arm64/boot/dts/axiado/ax3000.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..ea85ae8ca5dea5ab3288a2770b18d7aeb66cad03
--- /dev/null
+++ b/arch/arm64/boot/dts/axiado/ax3000.dtsi
@@ -0,0 +1,488 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021-25 Axiado Corporation (or its affiliates). All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/memreserve/ 0x3c0013a0 0x00000008;	/* cpu-release-addr */
+/ {
+	model = "Axiado AX3000";
+	interrupt-parent = <&gic500>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x0>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0x3c0013a0>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			next-level-cache = <&l2>;
+		};
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x1>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0x3c0013a0>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			next-level-cache = <&l2>;
+		};
+		cpu2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x2>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0x3c0013a0>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			next-level-cache = <&l2>;
+		};
+		cpu3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x3>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0x3c0013a0>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			next-level-cache = <&l2>;
+		};
+		l2: l2-cache0 {
+			compatible = "cache";
+			cache-size = <0x100000>;
+			cache-unified;
+			cache-line-size = <64>;
+			cache-sets = <1024>;
+			cache-level = <2>;
+		};
+	};
+
+	clocks {
+		clk_xin: clock-200000000 {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <200000000>;
+			clock-output-names = "clk_xin";
+		};
+		refclk: clock-125000000 {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <125000000>;
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		ranges;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		interrupt-parent = <&gic500>;
+
+		gic500: interrupt-controller@80300000 {
+			compatible = "arm,gic-v3";
+			reg = <0x00 0x80300000 0x00 0x10000>,
+				  <0x00 0x80380000 0x00 0x80000>;
+			ranges;
+			#interrupt-cells = <3>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			interrupt-controller;
+			#redistributor-regions = <1>;
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		/* GPIO Controller banks 0 - 7 */
+		gpio0: gpio-controller@80500000 {
+			compatible = "cdns,gpio-r1p02";
+			reg = <0x00 0x80500000 0x00  0x400>;
+			clocks = <&refclk>;
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			status = "disabled";
+		};
+		gpio1: gpio-controller@80580000 {
+			compatible = "cdns,gpio-r1p02";
+			reg = <0x00 0x80580000 0x00  0x400>;
+			clocks = <&refclk>;
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			status = "disabled";
+		};
+		gpio2: gpio-controller@80600000 {
+			compatible = "cdns,gpio-r1p02";
+			reg = <0x00 0x80600000 0x00  0x400>;
+			clocks = <&refclk>;
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			status = "disabled";
+		};
+		gpio3: gpio-controller@80680000 {
+			compatible = "cdns,gpio-r1p02";
+			reg = <0x00 0x80680000 0x00  0x400>;
+			clocks = <&refclk>;
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			status = "disabled";
+		};
+		gpio4: gpio-controller@80700000 {
+			compatible = "cdns,gpio-r1p02";
+			reg = <0x00 0x80700000 0x00  0x400>;
+			clocks = <&refclk>;
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			status = "disabled";
+		};
+		gpio5: gpio-controller@80780000 {
+			compatible = "cdns,gpio-r1p02";
+			reg = <0x00 0x80780000 0x00  0x400>;
+			clocks = <&refclk>;
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			status = "disabled";
+		};
+		gpio6: gpio-controller@80800000 {
+			compatible = "cdns,gpio-r1p02";
+			reg = <0x00 0x80800000 0x00  0x400>;
+			clocks = <&refclk>;
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			status = "disabled";
+		};
+		gpio7: gpio-controller@80880000 {
+			compatible = "cdns,gpio-r1p02";
+			reg = <0x00 0x80880000 0x00  0x400>;
+			clocks = <&refclk>;
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			status = "disabled";
+		};
+
+		/* I3C Controller 0 - 16 */
+		i3c0: i3c@80500400 {
+			compatible = "cdns,i3c-master";
+			reg = <0x00 0x80500400 0x00 0x400>;
+			clocks = <&refclk &clk_xin>;
+			clock-names = "pclk", "sysclk";
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+			i2c-scl-hz = <100000>;
+			i3c-scl-hz = <400000>;
+			#address-cells = <3>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		i3c1: i3c@80500800 {
+			compatible = "cdns,i3c-master";
+			reg = <0x00 0x80500800 0x00 0x400>;
+			clocks = <&refclk &clk_xin>;
+			clock-names = "pclk", "sysclk";
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+			i2c-scl-hz = <100000>;
+			i3c-scl-hz = <400000>;
+			#address-cells = <3>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		i3c2: i3c@80580400 {
+			compatible = "cdns,i3c-master";
+			reg = <0x00 0x80580400 0x00 0x400>;
+			clocks = <&refclk &clk_xin>;
+			clock-names = "pclk", "sysclk";
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+			i2c-scl-hz = <100000>;
+			i3c-scl-hz = <400000>;
+			#address-cells = <3>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		i3c3: i3c@80580800 {
+			compatible = "cdns,i3c-master";
+			reg = <0x00 0x80580800 0x00 0x400>;
+			clocks = <&refclk &clk_xin>;
+			clock-names = "pclk", "sysclk";
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+			i2c-scl-hz = <100000>;
+			i3c-scl-hz = <400000>;
+			#address-cells = <3>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		i3c4: i3c@80600400 {
+			compatible = "cdns,i3c-master";
+			reg = <0x00 0x80600400 0x00 0x400>;
+			clocks = <&refclk &clk_xin>;
+			clock-names = "pclk", "sysclk";
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+			i2c-scl-hz = <100000>;
+			i3c-scl-hz = <400000>;
+			#address-cells = <3>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		i3c5: i3c@80600800 {
+			compatible = "cdns,i3c-master";
+			reg = <0x00 0x80600800 0x00 0x400>;
+			clocks = <&refclk &clk_xin>;
+			clock-names = "pclk", "sysclk";
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+			i2c-scl-hz = <100000>;
+			i3c-scl-hz = <400000>;
+			#address-cells = <3>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		i3c6: i3c@80680400 {
+			compatible = "cdns,i3c-master";
+			reg = <0x00 0x80680400 0x00 0x400>;
+			clocks = <&refclk &clk_xin>;
+			clock-names = "pclk", "sysclk";
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+			i2c-scl-hz = <100000>;
+			i3c-scl-hz = <400000>;
+			#address-cells = <3>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		i3c7: i3c@80680800 {
+			compatible = "cdns,i3c-master";
+			reg = <0x00 0x80680800 0x00 0x400>;
+			clocks = <&refclk &clk_xin>;
+			clock-names = "pclk", "sysclk";
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+			i2c-scl-hz = <100000>;
+			i3c-scl-hz = <400000>;
+			#address-cells = <3>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		i3c8: i3c@80700400 {
+			compatible = "cdns,i3c-master";
+			reg = <0x00 0x80700400 0x00 0x400>;
+			clocks = <&refclk &clk_xin>;
+			clock-names = "pclk", "sysclk";
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+			i2c-scl-hz = <100000>;
+			i3c-scl-hz = <400000>;
+			#address-cells = <3>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		i3c9: i3c@80700800 {
+			compatible = "cdns,i3c-master";
+			reg = <0x00 0x80700800 0x00 0x400>;
+			clocks = <&refclk &clk_xin>;
+			clock-names = "pclk", "sysclk";
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+			i2c-scl-hz = <100000>;
+			i3c-scl-hz = <400000>;
+			#address-cells = <3>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		i3c10: i3c@80780400 {
+			compatible = "cdns,i3c-master";
+			reg = <0x00 0x80780400 0x00 0x400>;
+			clocks = <&refclk &clk_xin>;
+			clock-names = "pclk", "sysclk";
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+			i2c-scl-hz = <100000>;
+			i3c-scl-hz = <400000>;
+			#address-cells = <3>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		i3c11: i3c@80780800 {
+			compatible = "cdns,i3c-master";
+			reg = <0x00 0x80780800 0x00 0x400>;
+			clocks = <&refclk &clk_xin>;
+			clock-names = "pclk", "sysclk";
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+			i2c-scl-hz = <100000>;
+			i3c-scl-hz = <400000>;
+			#address-cells = <3>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		i3c12: i3c@80800400 {
+			compatible = "cdns,i3c-master";
+			reg = <0x00 0x80800400 0x00 0x400>;
+			clocks = <&refclk &clk_xin>;
+			clock-names = "pclk", "sysclk";
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+			i2c-scl-hz = <100000>;
+			i3c-scl-hz = <400000>;
+			#address-cells = <3>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		i3c13: i3c@80800800 {
+			compatible = "cdns,i3c-master";
+			reg = <0x00 0x80800800 0x00 0x400>;
+			clocks = <&refclk &clk_xin>;
+			clock-names = "pclk", "sysclk";
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+			i2c-scl-hz = <100000>;
+			i3c-scl-hz = <400000>;
+			#address-cells = <3>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		i3c14: i3c@80880400 {
+			compatible = "cdns,i3c-master";
+			reg = <0x00 0x80880400 0x00 0x400>;
+			clocks = <&refclk &clk_xin>;
+			clock-names = "pclk", "sysclk";
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+			i2c-scl-hz = <100000>;
+			i3c-scl-hz = <400000>;
+			#address-cells = <3>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		i3c15: i3c@80880800 {
+			compatible = "cdns,i3c-master";
+			reg = <0x00 0x80880800 0x00 0x400>;
+			clocks = <&refclk &clk_xin>;
+			clock-names = "pclk", "sysclk";
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+			i2c-scl-hz = <100000>;
+			i3c-scl-hz = <400000>;
+			#address-cells = <3>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		i3c16: i3c@80620400 {
+			compatible = "cdns,i3c-master";
+			reg = <0x00 0x80620400 0x00 0x400>;
+			clocks = <&refclk &clk_xin>;
+			clock-names = "pclk", "sysclk";
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+			i2c-scl-hz = <100000>;
+			i3c-scl-hz = <400000>;
+			#address-cells = <3>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+		uart0: serial@80520000 {
+			compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
+			reg = <0x00 0x80520000 0x00 0x100>;
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "uart_clk", "pclk";
+			clocks = <&refclk &refclk>;
+			status = "disabled";
+		};
+		uart1: serial@805a0000 {
+			compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
+			reg = <0x00 0x805A0000 0x00 0x100>;
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "uart_clk", "pclk";
+			clocks = <&refclk &refclk>;
+			status = "disabled";
+		};
+		uart2: serial@80620000 {
+			compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
+			reg = <0x00 0x80620000 0x00 0x100>;
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "uart_clk", "pclk";
+			clocks = <&refclk &refclk>;
+			status = "disabled";
+		};
+		uart3: serial@80520800 {
+			compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
+			reg = <0x00 0x80520800 0x00 0x100>;
+			interrupt-parent = <&gic500>;
+			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "uart_clk", "pclk";
+			clocks = <&refclk &refclk>;
+			status = "disabled";
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupt-parent = <&gic500>;
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
+			   <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
+	};
+};

-- 
2.25.1

On 23/06/2025 19:28, Harshit Shah wrote:
> Add initial device tree support for the AX3000 SoC and its evaluation
> platform. The AX3000 is a multi-core SoC featuring 4 Cortex-A53 cores,
> Secure Vault, AI Engine and Firewall.
> 
> This commit adds support for Cortex-A53 CPUs, timer, UARTs, and I3C
> controllers on the AX3000 evaluation board.
> 
> Signed-off-by: Harshit Shah <hshah@axiado.com>
> ---
>  arch/arm64/boot/dts/Makefile              |   1 +
>  arch/arm64/boot/dts/axiado/Makefile       |   2 +
>  arch/arm64/boot/dts/axiado/ax3000-evk.dts |  79 +++++
>  arch/arm64/boot/dts/axiado/ax3000.dtsi    | 488 ++++++++++++++++++++++++++++++
>  4 files changed, 570 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index 79b73a21ddc22b17308554e502f8207392935b45..47dd8a1a7960d179ee28969a1d6750bfa0d73da1 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -9,6 +9,7 @@ subdir-y += amlogic
>  subdir-y += apm
>  subdir-y += apple
>  subdir-y += arm
> +subdir-y += axiado
>  subdir-y += bitmain
>  subdir-y += blaize
>  subdir-y += broadcom
> diff --git a/arch/arm64/boot/dts/axiado/Makefile b/arch/arm64/boot/dts/axiado/Makefile
> new file mode 100644
> index 0000000000000000000000000000000000000000..6676ad07db6129f8b333b0feffee705d272517c2
> --- /dev/null
> +++ b/arch/arm64/boot/dts/axiado/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_AXIADO) += ax3000-evk.dtb
> diff --git a/arch/arm64/boot/dts/axiado/ax3000-evk.dts b/arch/arm64/boot/dts/axiado/ax3000-evk.dts
> new file mode 100644
> index 0000000000000000000000000000000000000000..cc3bcf681c32430d251f20f6d52905423c182f3b
> --- /dev/null
> +++ b/arch/arm64/boot/dts/axiado/ax3000-evk.dts
> @@ -0,0 +1,79 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2021-25 Axiado Corporation (or its affiliates). All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include "ax3000.dtsi"
> +
> +/ {
> +	model = "Axiado AX3000 EVK";
> +	compatible = "axiado,ax3000-evk", "axiado,ax3000";
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	aliases {
> +		serial3 = &uart3;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial3:115200";
> +	};
> +
> +	memory@0 {
> +		device_type = "memory";
> +		/* Cortex-A53 will use following memory map */
> +		reg = <0x00000000 0x3D000000 0x00000000 0x23000000>,

Lowercase hex, see DTS coding style.

> +		      <0x00000004 0x00000000 0x00000000 0x80000000>;
> +	};
> +};
> +
> +/* GPIO bank 0 - 7 */
> +&gpio0 {
> +	status = "okay";
> +};
> +
> +&gpio1 {
> +	status = "okay";
> +};
> +
> +&gpio2 {
> +	status = "okay";
> +};
> +
> +&gpio3 {
> +	status = "okay";
> +};
> +
> +&gpio4 {
> +	status = "okay";
> +};
> +
> +&gpio5 {
> +	status = "okay";
> +};
> +
> +&gpio6 {
> +	status = "okay";
> +};
> +
> +&gpio7 {
> +	status = "okay";
> +};
> +
> +&uart0 {
> +	status = "okay";
> +};
> +
> +&uart1 {
> +	status = "okay";
> +};
> +
> +&uart2 {
> +	status = "okay";
> +};
> +
> +&uart3 {
> +	status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/axiado/ax3000.dtsi b/arch/arm64/boot/dts/axiado/ax3000.dtsi
> new file mode 100644
> index 0000000000000000000000000000000000000000..ea85ae8ca5dea5ab3288a2770b18d7aeb66cad03
> --- /dev/null
> +++ b/arch/arm64/boot/dts/axiado/ax3000.dtsi
> @@ -0,0 +1,488 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2021-25 Axiado Corporation (or its affiliates). All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/memreserve/ 0x3c0013a0 0x00000008;	/* cpu-release-addr */
> +/ {
> +	model = "Axiado AX3000";
> +	interrupt-parent = <&gic500>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	cpus {
> +		#address-cells = <2>;
> +		#size-cells = <0>;
> +
> +		cpu0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a53";
> +			reg = <0x0 0x0>;
> +			enable-method = "spin-table";
> +			cpu-release-addr = <0x0 0x3c0013a0>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			i-cache-size = <0x8000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <256>;
> +			next-level-cache = <&l2>;
> +		};

Missing blank line between each new node. See DTS coding style.

> +		cpu1: cpu@1 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a53";
> +			reg = <0x0 0x1>;
> +			enable-method = "spin-table";
> +			cpu-release-addr = <0x0 0x3c0013a0>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			i-cache-size = <0x8000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <256>;
> +			next-level-cache = <&l2>;
> +		};
> +		cpu2: cpu@2 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a53";
> +			reg = <0x0 0x2>;
> +			enable-method = "spin-table";
> +			cpu-release-addr = <0x0 0x3c0013a0>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			i-cache-size = <0x8000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <256>;
> +			next-level-cache = <&l2>;
> +		};
> +		cpu3: cpu@3 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a53";
> +			reg = <0x0 0x3>;
> +			enable-method = "spin-table";
> +			cpu-release-addr = <0x0 0x3c0013a0>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			i-cache-size = <0x8000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <256>;
> +			next-level-cache = <&l2>;
> +		};
> +		l2: l2-cache0 {
> +			compatible = "cache";
> +			cache-size = <0x100000>;
> +			cache-unified;
> +			cache-line-size = <64>;
> +			cache-sets = <1024>;
> +			cache-level = <2>;
> +		};
> +	};
> +
> +	clocks {
> +		clk_xin: clock-200000000 {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +			clock-frequency = <200000000>;
> +			clock-output-names = "clk_xin";
> +		};
> +		refclk: clock-125000000 {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +			clock-frequency = <125000000>;
> +		};
> +	};
> +
> +	soc {
> +		compatible = "simple-bus";
> +		ranges;
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		interrupt-parent = <&gic500>;
> +
> +		gic500: interrupt-controller@80300000 {
> +			compatible = "arm,gic-v3";
> +			reg = <0x00 0x80300000 0x00 0x10000>,
> +				  <0x00 0x80380000 0x00 0x80000>;

Does not look aligned.

> +			ranges;
> +			#interrupt-cells = <3>;
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			interrupt-controller;
> +			#redistributor-regions = <1>;
> +			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +
> +		/* GPIO Controller banks 0 - 7 */
> +		gpio0: gpio-controller@80500000 {
> +			compatible = "cdns,gpio-r1p02";
> +			reg = <0x00 0x80500000 0x00  0x400>;

Only one space, not double space.

> +			clocks = <&refclk>;
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			status = "disabled";
> +		};

Please follow DTS coding style.

> +		gpio1: gpio-controller@80580000 {
> +			compatible = "cdns,gpio-r1p02";

This should not be accepted without specific compatible, but that's some
old binding so maybe matters less. Anyway, if you ever need quirk or
custom properties they I will reject them based on what you claim here.


> +			reg = <0x00 0x80580000 0x00  0x400>;
> +			clocks = <&refclk>;
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			status = "disabled";
> +		};
> +		gpio2: gpio-controller@80600000 {
> +			compatible = "cdns,gpio-r1p02";
> +			reg = <0x00 0x80600000 0x00  0x400>;
> +			clocks = <&refclk>;
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			status = "disabled";
> +		};
> +		gpio3: gpio-controller@80680000 {
> +			compatible = "cdns,gpio-r1p02";
> +			reg = <0x00 0x80680000 0x00  0x400>;
> +			clocks = <&refclk>;
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			status = "disabled";
> +		};
> +		gpio4: gpio-controller@80700000 {
> +			compatible = "cdns,gpio-r1p02";
> +			reg = <0x00 0x80700000 0x00  0x400>;
> +			clocks = <&refclk>;
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			status = "disabled";
> +		};
> +		gpio5: gpio-controller@80780000 {
> +			compatible = "cdns,gpio-r1p02";
> +			reg = <0x00 0x80780000 0x00  0x400>;
> +			clocks = <&refclk>;
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			status = "disabled";
> +		};
> +		gpio6: gpio-controller@80800000 {
> +			compatible = "cdns,gpio-r1p02";
> +			reg = <0x00 0x80800000 0x00  0x400>;
> +			clocks = <&refclk>;
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			status = "disabled";
> +		};
> +		gpio7: gpio-controller@80880000 {
> +			compatible = "cdns,gpio-r1p02";
> +			reg = <0x00 0x80880000 0x00  0x400>;
> +			clocks = <&refclk>;
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			status = "disabled";
> +		};
> +
> +		/* I3C Controller 0 - 16 */
> +		i3c0: i3c@80500400 {
> +			compatible = "cdns,i3c-master";
> +			reg = <0x00 0x80500400 0x00 0x400>;
> +			clocks = <&refclk &clk_xin>;
> +			clock-names = "pclk", "sysclk";
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
> +			i2c-scl-hz = <100000>;
> +			i3c-scl-hz = <400000>;
> +			#address-cells = <3>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +		i3c1: i3c@80500800 {
> +			compatible = "cdns,i3c-master";
> +			reg = <0x00 0x80500800 0x00 0x400>;
> +			clocks = <&refclk &clk_xin>;
> +			clock-names = "pclk", "sysclk";
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
> +			i2c-scl-hz = <100000>;
> +			i3c-scl-hz = <400000>;
> +			#address-cells = <3>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +		i3c2: i3c@80580400 {
> +			compatible = "cdns,i3c-master";
> +			reg = <0x00 0x80580400 0x00 0x400>;
> +			clocks = <&refclk &clk_xin>;
> +			clock-names = "pclk", "sysclk";
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
> +			i2c-scl-hz = <100000>;
> +			i3c-scl-hz = <400000>;
> +			#address-cells = <3>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +		i3c3: i3c@80580800 {
> +			compatible = "cdns,i3c-master";
> +			reg = <0x00 0x80580800 0x00 0x400>;
> +			clocks = <&refclk &clk_xin>;
> +			clock-names = "pclk", "sysclk";
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
> +			i2c-scl-hz = <100000>;
> +			i3c-scl-hz = <400000>;
> +			#address-cells = <3>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +		i3c4: i3c@80600400 {
> +			compatible = "cdns,i3c-master";
> +			reg = <0x00 0x80600400 0x00 0x400>;
> +			clocks = <&refclk &clk_xin>;
> +			clock-names = "pclk", "sysclk";
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
> +			i2c-scl-hz = <100000>;
> +			i3c-scl-hz = <400000>;
> +			#address-cells = <3>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +		i3c5: i3c@80600800 {
> +			compatible = "cdns,i3c-master";
> +			reg = <0x00 0x80600800 0x00 0x400>;
> +			clocks = <&refclk &clk_xin>;
> +			clock-names = "pclk", "sysclk";
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
> +			i2c-scl-hz = <100000>;
> +			i3c-scl-hz = <400000>;
> +			#address-cells = <3>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +		i3c6: i3c@80680400 {
> +			compatible = "cdns,i3c-master";
> +			reg = <0x00 0x80680400 0x00 0x400>;
> +			clocks = <&refclk &clk_xin>;
> +			clock-names = "pclk", "sysclk";
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
> +			i2c-scl-hz = <100000>;
> +			i3c-scl-hz = <400000>;
> +			#address-cells = <3>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +		i3c7: i3c@80680800 {
> +			compatible = "cdns,i3c-master";
> +			reg = <0x00 0x80680800 0x00 0x400>;
> +			clocks = <&refclk &clk_xin>;
> +			clock-names = "pclk", "sysclk";
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> +			i2c-scl-hz = <100000>;
> +			i3c-scl-hz = <400000>;
> +			#address-cells = <3>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +		i3c8: i3c@80700400 {
> +			compatible = "cdns,i3c-master";
> +			reg = <0x00 0x80700400 0x00 0x400>;
> +			clocks = <&refclk &clk_xin>;
> +			clock-names = "pclk", "sysclk";
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
> +			i2c-scl-hz = <100000>;
> +			i3c-scl-hz = <400000>;
> +			#address-cells = <3>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +		i3c9: i3c@80700800 {
> +			compatible = "cdns,i3c-master";
> +			reg = <0x00 0x80700800 0x00 0x400>;
> +			clocks = <&refclk &clk_xin>;
> +			clock-names = "pclk", "sysclk";
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> +			i2c-scl-hz = <100000>;
> +			i3c-scl-hz = <400000>;
> +			#address-cells = <3>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +		i3c10: i3c@80780400 {
> +			compatible = "cdns,i3c-master";
> +			reg = <0x00 0x80780400 0x00 0x400>;
> +			clocks = <&refclk &clk_xin>;
> +			clock-names = "pclk", "sysclk";
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
> +			i2c-scl-hz = <100000>;
> +			i3c-scl-hz = <400000>;
> +			#address-cells = <3>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +		i3c11: i3c@80780800 {
> +			compatible = "cdns,i3c-master";
> +			reg = <0x00 0x80780800 0x00 0x400>;
> +			clocks = <&refclk &clk_xin>;
> +			clock-names = "pclk", "sysclk";
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
> +			i2c-scl-hz = <100000>;
> +			i3c-scl-hz = <400000>;
> +			#address-cells = <3>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +		i3c12: i3c@80800400 {
> +			compatible = "cdns,i3c-master";
> +			reg = <0x00 0x80800400 0x00 0x400>;
> +			clocks = <&refclk &clk_xin>;
> +			clock-names = "pclk", "sysclk";
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
> +			i2c-scl-hz = <100000>;
> +			i3c-scl-hz = <400000>;
> +			#address-cells = <3>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +		i3c13: i3c@80800800 {
> +			compatible = "cdns,i3c-master";
> +			reg = <0x00 0x80800800 0x00 0x400>;
> +			clocks = <&refclk &clk_xin>;
> +			clock-names = "pclk", "sysclk";
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> +			i2c-scl-hz = <100000>;
> +			i3c-scl-hz = <400000>;
> +			#address-cells = <3>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +		i3c14: i3c@80880400 {
> +			compatible = "cdns,i3c-master";
> +			reg = <0x00 0x80880400 0x00 0x400>;
> +			clocks = <&refclk &clk_xin>;
> +			clock-names = "pclk", "sysclk";
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
> +			i2c-scl-hz = <100000>;
> +			i3c-scl-hz = <400000>;
> +			#address-cells = <3>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +		i3c15: i3c@80880800 {
> +			compatible = "cdns,i3c-master";
> +			reg = <0x00 0x80880800 0x00 0x400>;
> +			clocks = <&refclk &clk_xin>;
> +			clock-names = "pclk", "sysclk";
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
> +			i2c-scl-hz = <100000>;
> +			i3c-scl-hz = <400000>;
> +			#address-cells = <3>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +		i3c16: i3c@80620400 {
> +			compatible = "cdns,i3c-master";
> +			reg = <0x00 0x80620400 0x00 0x400>;
> +			clocks = <&refclk &clk_xin>;
> +			clock-names = "pclk", "sysclk";
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
> +			i2c-scl-hz = <100000>;
> +			i3c-scl-hz = <400000>;
> +			#address-cells = <3>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +		uart0: serial@80520000 {

Looks like not ordered by unit address. What is the ordering rule you
are going to adopt for entire arch?

> +			compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";

NAK, you do not have xlnx here. Look at your SoC: name of vendor is
axiado. Not xlnx. How is your SoC called? Also zynqmp? You cannot just
randomly pick any compatibles and stuff them around.

Please carefully read writing bindings from DT directory.


> +			reg = <0x00 0x80520000 0x00 0x100>;
> +			interrupt-parent = <&gic500>;
> +			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
> +			clock-names = "uart_clk", "pclk";
> +			clocks = <&refclk &refclk>;
> +			status = "disabled";
> +		};
Best regards,
Krzysztof

Thank you for the reviews. I have some questions/feedback to clarify 
before I fix some of them.

On 6/23/2025 11:45 PM, Krzysztof Kozlowski wrote:
>
> On 23/06/2025 19:28, Harshit Shah wrote:
>> +                     clocks = <&refclk>;
>> +                     interrupt-parent = <&gic500>;
>> +                     interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
>> +                     gpio-controller;
>> +                     #gpio-cells = <2>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <2>;
>> +                     status = "disabled";
>> +             };
> Please follow DTS coding style.

Sorry, I didn't got this comment. Is this for the spaces between the 
nodes or something else?

The current GPIO node is as follows:

gpio0: gpio-controller@80500000 {
                         compatible = "cdns,gpio-r1p02";
                         reg = <0x00 0x80500000 0x00 0x400>;
                         clocks = <&refclk>;
                         interrupt-parent = <&gic500>;
                         interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
                         gpio-controller;
                         #gpio-cells = <2>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
                         status = "disabled";
                 };

I checked the document: 
https://elixir.bootlin.com/linux/v6.15/source/Documentation/devicetree/bindings/dts-coding-style.rst#L112.

>
>> +             gpio1: gpio-controller@80580000 {
>> +                     compatible = "cdns,gpio-r1p02";
> This should not be accepted without specific compatible, but that's some
> old binding so maybe matters less. Anyway, if you ever need quirk or
> custom properties they I will reject them based on what you claim here.

Yes, we are not changing anything on this driver. Is it okay?


>
>
>> +             i3c16: i3c@80620400 {
>> +                     compatible = "cdns,i3c-master";
>> +                     reg = <0x00 0x80620400 0x00 0x400>;
>> +                     clocks = <&refclk &clk_xin>;
>> +                     clock-names = "pclk", "sysclk";
>> +                     interrupt-parent = <&gic500>;
>> +                     interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
>> +                     i2c-scl-hz = <100000>;
>> +                     i3c-scl-hz = <400000>;
>> +                     #address-cells = <3>;
>> +                     #size-cells = <0>;
>> +                     status = "disabled";
>> +             };
>> +             uart0: serial@80520000 {
> Looks like not ordered by unit address. What is the ordering rule you
> are going to adopt for entire arch?

Apologies for the confusion. I should have updated in last patch-set 
comments.

We are following alphabetical ordering rule. In those we are grouping 
some nodes together based on the numbers.

cpus

clocks

soc {

    gic500 { }

    gpio0-7 { }

    i3c0-16 { }

    uart0-3 { }

}

timer


Is this okay?

>
>> +                     compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
> NAK, you do not have xlnx here. Look at your SoC: name of vendor is
> axiado. Not xlnx. How is your SoC called? Also zynqmp? You cannot just
> randomly pick any compatibles and stuff them around.
>
> Please carefully read writing bindings from DT directory.


We are using the "cdns,uart-r1p12" for the UART. However, that alone 
can't be added alone in the compatible as per the DT bindings doc.

So that's the reason we have used the other node. However, which is not 
proper, understood your point. Thank you for the same.


This driver' on of the compatible is "cdns,uart-r1p12". Ref: 
https://elixir.bootlin.com/linux/v6.15/source/drivers/tty/serial/xilinx_uartps.c#L1598. 


Is it okay if we edit this file 
(https://elixir.bootlin.com/linux/v6.15/source/Documentation/devicetree/bindings/serial/cdns,uart.yaml#L12) 


to have the supported "OneOf" as "cdns,uart-r1p12" ?


Regards,

Harshit.

On 25/06/2025 04:16, Harshit Shah wrote:
> Thank you for the reviews. I have some questions/feedback to clarify 
> before I fix some of them.
> 
> On 6/23/2025 11:45 PM, Krzysztof Kozlowski wrote:
>>
>> On 23/06/2025 19:28, Harshit Shah wrote:
>>> +                     clocks = <&refclk>;
>>> +                     interrupt-parent = <&gic500>;
>>> +                     interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
>>> +                     gpio-controller;
>>> +                     #gpio-cells = <2>;
>>> +                     interrupt-controller;
>>> +                     #interrupt-cells = <2>;
>>> +                     status = "disabled";
>>> +             };
>> Please follow DTS coding style.
> 
> Sorry, I didn't got this comment. Is this for the spaces between the 
> nodes or something else?
> 
> The current GPIO node is as follows:

There is always, always line break between nodes.

> 
> gpio0: gpio-controller@80500000 {
>                          compatible = "cdns,gpio-r1p02";
>                          reg = <0x00 0x80500000 0x00 0x400>;
>                          clocks = <&refclk>;
>                          interrupt-parent = <&gic500>;
>                          interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
>                          gpio-controller;
>                          #gpio-cells = <2>;
>                          interrupt-controller;
>                          #interrupt-cells = <2>;
>                          status = "disabled";
>                  };
> 
> I checked the document: 
> https://elixir.bootlin.com/linux/v6.15/source/Documentation/devicetree/bindings/dts-coding-style.rst#L112.
> 
>>
>>> +             gpio1: gpio-controller@80580000 {
>>> +                     compatible = "cdns,gpio-r1p02";
>> This should not be accepted without specific compatible, but that's some
>> old binding so maybe matters less. Anyway, if you ever need quirk or
>> custom properties they I will reject them based on what you claim here.
> 
> Yes, we are not changing anything on this driver. Is it okay?

I meant for future. I would expect to follow writing bindings now, so
have front specific compatible, but if you do not then whatever issues
you have in the future with this driver, they should be rejected, right?

> 
> 
>>
>>
>>> +             i3c16: i3c@80620400 {
>>> +                     compatible = "cdns,i3c-master";
>>> +                     reg = <0x00 0x80620400 0x00 0x400>;
>>> +                     clocks = <&refclk &clk_xin>;
>>> +                     clock-names = "pclk", "sysclk";
>>> +                     interrupt-parent = <&gic500>;
>>> +                     interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
>>> +                     i2c-scl-hz = <100000>;
>>> +                     i3c-scl-hz = <400000>;
>>> +                     #address-cells = <3>;
>>> +                     #size-cells = <0>;
>>> +                     status = "disabled";
>>> +             };
>>> +             uart0: serial@80520000 {
>> Looks like not ordered by unit address. What is the ordering rule you
>> are going to adopt for entire arch?
> 
> Apologies for the confusion. I should have updated in last patch-set 
> comments.
> 
> We are following alphabetical ordering rule. In those we are grouping 
> some nodes together based on the numbers.
> 
> cpus
> 
> clocks
> 
> soc {
> 
>     gic500 { }
> 
>     gpio0-7 { }
> 
>     i3c0-16 { }
> 
>     uart0-3 { }
> 
> }
> 
> timer
> 
> 
> Is this okay?

alphabetical ordering is not mentioned in dts coding style. Maybe it
should, but I think the only user of second style with grouping nodes -
Renesas - still uses ordering by unit address in general.

The trouble with your approach is that if you ever need to change the
name, you will need to re-order and move entire node.

Anyway, not a problem for me.

> 
>>
>>> +                     compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
>> NAK, you do not have xlnx here. Look at your SoC: name of vendor is
>> axiado. Not xlnx. How is your SoC called? Also zynqmp? You cannot just
>> randomly pick any compatibles and stuff them around.
>>
>> Please carefully read writing bindings from DT directory.
> 
> 
> We are using the "cdns,uart-r1p12" for the UART. However, that alone 
> can't be added alone in the compatible as per the DT bindings doc.

Exactly. See writing bindings... or any guides/talks.


Best regards,
Krzysztof

On 6/24/2025 11:05 PM, Krzysztof Kozlowski wrote:
> CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
>
>
> On 25/06/2025 04:16, Harshit Shah wrote:
>> gpio0: gpio-controller@80500000 {
>>                           compatible = "cdns,gpio-r1p02";
>>                           reg = <0x00 0x80500000 0x00 0x400>;
>>                           clocks = <&refclk>;
>>                           interrupt-parent = <&gic500>;
>>                           interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
>>                           gpio-controller;
>>                           #gpio-cells = <2>;
>>                           interrupt-controller;
>>                           #interrupt-cells = <2>;
>>                           status = "disabled";
>>                   };
>>
>> I checked the document:
>> https://elixir.bootlin.com/linux/v6.15/source/Documentation/devicetree/bindings/dts-coding-style.rst#L112.
>>
>>>> +             gpio1: gpio-controller@80580000 {
>>>> +                     compatible = "cdns,gpio-r1p02";
>>> This should not be accepted without specific compatible, but that's some
>>> old binding so maybe matters less. Anyway, if you ever need quirk or
>>> custom properties they I will reject them based on what you claim here.
>> Yes, we are not changing anything on this driver. Is it okay?
> I meant for future. I would expect to follow writing bindings now, so
> have front specific compatible, but if you do not then whatever issues
> you have in the future with this driver, they should be rejected, right?

Based on the another discussion for the UART node, we understood this 
better.

It would be better if we change this GPIO nodes to with the below 
compatible.

compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02".

>
>>
>>>
>>>> +             i3c16: i3c@80620400 {
>>>> +                     compatible = "cdns,i3c-master";
>>>> +                     reg = <0x00 0x80620400 0x00 0x400>;
>>>> +                     clocks = <&refclk &clk_xin>;
>>>> +                     clock-names = "pclk", "sysclk";
>>>> +                     interrupt-parent = <&gic500>;
>>>> +                     interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
>>>> +                     i2c-scl-hz = <100000>;
>>>> +                     i3c-scl-hz = <400000>;
>>>> +                     #address-cells = <3>;
>>>> +                     #size-cells = <0>;
>>>> +                     status = "disabled";
>>>> +             };
>>>> +             uart0: serial@80520000 {
>>> Looks like not ordered by unit address. What is the ordering rule you
>>> are going to adopt for entire arch?
>> Apologies for the confusion. I should have updated in last patch-set
>> comments.
>>
>> We are following alphabetical ordering rule. In those we are grouping
>> some nodes together based on the numbers.
>>
>> cpus
>>
>> clocks
>>
>> soc {
>>
>>      gic500 { }
>>
>>      gpio0-7 { }
>>
>>      i3c0-16 { }
>>
>>      uart0-3 { }
>>
>> }
>>
>> timer
>>
>>
>> Is this okay?
> alphabetical ordering is not mentioned in dts coding style. Maybe it
> should, but I think the only user of second style with grouping nodes -
> Renesas - still uses ordering by unit address in general.
>
> The trouble with your approach is that if you ever need to change the
> name, you will need to re-order and move entire node.
>
> Anyway, not a problem for me.

Okay, Thank you.


Regards,

Harshit.

On 6/24/2025 11:05 PM, Krzysztof Kozlowski wrote:
>>
>>
>>>> +                     compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
>>> NAK, you do not have xlnx here. Look at your SoC: name of vendor is
>>> axiado. Not xlnx. How is your SoC called? Also zynqmp? You cannot just
>>> randomly pick any compatibles and stuff them around.
>>>
>>> Please carefully read writing bindings from DT directory.
>>
>> We are using the "cdns,uart-r1p12" for the UART. However, that alone
>> can't be added alone in the compatible as per the DT bindings doc.
> Exactly. See writing bindings... or any guides/talks.

We will add the "compatible = "axiado,ax-uart", "cdns,uart-r1p12". We 
will append in the dt-bindings doc and driver.

Is this name look good?

On 26/06/2025 03:31, Harshit Shah wrote:
> On 6/24/2025 11:05 PM, Krzysztof Kozlowski wrote:
>>>
>>>
>>>>> +                     compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
>>>> NAK, you do not have xlnx here. Look at your SoC: name of vendor is
>>>> axiado. Not xlnx. How is your SoC called? Also zynqmp? You cannot just
>>>> randomly pick any compatibles and stuff them around.
>>>>
>>>> Please carefully read writing bindings from DT directory.
>>>
>>> We are using the "cdns,uart-r1p12" for the UART. However, that alone
>>> can't be added alone in the compatible as per the DT bindings doc.
>> Exactly. See writing bindings... or any guides/talks.
> 
> We will add the "compatible = "axiado,ax-uart", "cdns,uart-r1p12". We 
> will append in the dt-bindings doc and driver.
> 
> Is this name look good?

No, all compatibles for SoC must be SoC specific. Take any recent
Qualcomm SM8650 or SM8750 as example.

I asked to read writing bindings. Did you read it? It covers exactly
this case.

Best regards,
Krzysztof

On 6/26/2025 1:50 AM, Krzysztof Kozlowski wrote:
> CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
>
>
> On 26/06/2025 03:31, Harshit Shah wrote:
>> On 6/24/2025 11:05 PM, Krzysztof Kozlowski wrote:
>>>>
>>>>>> +                     compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
>>>>> NAK, you do not have xlnx here. Look at your SoC: name of vendor is
>>>>> axiado. Not xlnx. How is your SoC called? Also zynqmp? You cannot just
>>>>> randomly pick any compatibles and stuff them around.
>>>>>
>>>>> Please carefully read writing bindings from DT directory.
>>>> We are using the "cdns,uart-r1p12" for the UART. However, that alone
>>>> can't be added alone in the compatible as per the DT bindings doc.
>>> Exactly. See writing bindings... or any guides/talks.
>> We will add the "compatible = "axiado,ax-uart", "cdns,uart-r1p12". We
>> will append in the dt-bindings doc and driver.
>>
>> Is this name look good?
> No, all compatibles for SoC must be SoC specific. Take any recent
> Qualcomm SM8650 or SM8750 as example.
>
> I asked to read writing bindings. Did you read it? It covers exactly
> this case.
>
> Best regards,
> Krzysztof


Extremely sorry for the last reply. It got messed up in formatting, 
re-sending the same.


Thank you for the references.

Yes, I missed the point in the writing bindings doc. It says the following:


"For sub-blocks/components of bigger device (e.g. SoC blocks) use rather 
device-based compatible (e.g. SoC-based compatible),

  instead of custom versioning of that component. For example use 
"vendor,soc1234-i2c" instead of "vendor,i2c-v2"."


(Ref: 
https://elixir.bootlin.com/linux/v6.15.3/source/Documentation/devicetree/bindings/writing-bindings.rst#L79) 


# We need to add the full SoC name instead of versioning. e.g. 
compatible should contain full SoC name ax3000.


Another example, we have seen is the designware I2C IP is used by MSCC, 
ocelot chipset.

It is showing as below in the following: 
(https://elixir.bootlin.com/linux/v6.16-rc3/source/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml) 


     i2c@100400 {

       compatible = "mscc,ocelot-i2c", "snps,designware-i2c";

       reg = <0x100400 0x100>, <0x198 0x8>;

       pinctrl-0 = <&i2c_pins>;

       pinctrl-names = "default";

       interrupts = <8>;

       clocks = <&ahb_clk>;

     };


# We will add this compatible in the existing driver 
(drivers/tty/serial/xilinx_uartps.c) &

bindings (Documentation/devicetree/bindings/serial/cdns,uart.yaml) since 
the IP is common.


As per the above examples,  I see two types of bindings.

1. compatible = "axiado,ax3000-uart", "cdns,uart-r1p12"

OR

2. compatible = "axiado,ax3000-uart"

Can you please help for this options? Apologies for the long thread again.


Regards,

Harshit.

On 27/06/2025 02:47, Harshit Shah wrote:
>>> Is this name look good?
>> No, all compatibles for SoC must be SoC specific. Take any recent
>> Qualcomm SM8650 or SM8750 as example.
>>
>> I asked to read writing bindings. Did you read it? It covers exactly
>> this case.
>>
>> Best regards,
>> Krzysztof
> 
> 
> Extremely sorry for the last reply. It got messed up in formatting, 
> re-sending the same.
> 
> 
> Thank you for the references.
> 
> Yes, I missed the point in the writing bindings doc. It says the following:
> 
> 
> "For sub-blocks/components of bigger device (e.g. SoC blocks) use rather 
> device-based compatible (e.g. SoC-based compatible),
> 
>   instead of custom versioning of that component. For example use 
> "vendor,soc1234-i2c" instead of "vendor,i2c-v2"."
> 
> 
> (Ref: 
> https://elixir.bootlin.com/linux/v6.15.3/source/Documentation/devicetree/bindings/writing-bindings.rst#L79) 
> 
> 
> # We need to add the full SoC name instead of versioning. e.g. 
> compatible should contain full SoC name ax3000.

Yes.

> 
> 
> Another example, we have seen is the designware I2C IP is used by MSCC, 
> ocelot chipset.
> 
> It is showing as below in the following: 
> (https://elixir.bootlin.com/linux/v6.16-rc3/source/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml) 
> 
> 
>      i2c@100400 {
> 
>        compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
> 
>        reg = <0x100400 0x100>, <0x198 0x8>;
> 
>        pinctrl-0 = <&i2c_pins>;
> 
>        pinctrl-names = "default";
> 
>        interrupts = <8>;
> 
>        clocks = <&ahb_clk>;
> 
>      };
> 
> 
> # We will add this compatible in the existing driver 
> (drivers/tty/serial/xilinx_uartps.c) &
> 
> bindings (Documentation/devicetree/bindings/serial/cdns,uart.yaml) since 
> the IP is common.
> 
> 
> As per the above examples,  I see two types of bindings.
> 
> 1. compatible = "axiado,ax3000-uart", "cdns,uart-r1p12"


This one. Thank you.


Best regards,
Krzysztof

On 6/26/2025 1:50 AM, Krzysztof Kozlowski wrote:
> CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
>
>
> On 26/06/2025 03:31, Harshit Shah wrote:
>> On 6/24/2025 11:05 PM, Krzysztof Kozlowski wrote:
>>>>
>>>>>> +                     compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
>>>>> NAK, you do not have xlnx here. Look at your SoC: name of vendor is
>>>>> axiado. Not xlnx. How is your SoC called? Also zynqmp? You cannot just
>>>>> randomly pick any compatibles and stuff them around.
>>>>>
>>>>> Please carefully read writing bindings from DT directory.
>>>> We are using the "cdns,uart-r1p12" for the UART. However, that alone
>>>> can't be added alone in the compatible as per the DT bindings doc.
>>> Exactly. See writing bindings... or any guides/talks.
>> We will add the "compatible = "axiado,ax-uart", "cdns,uart-r1p12". We
>> will append in the dt-bindings doc and driver.
>>
>> Is this name look good?
> No, all compatibles for SoC must be SoC specific. Take any recent
> Qualcomm SM8650 or SM8750 as example.
>
> I asked to read writing bindings. Did you read it? It covers exactly
> this case.
>
Thank you for the references.

Yes, I I missed the point in the writing bindings doc. It says the 
following:

" For sub-blocks/components of bigger device (e.g. SoC blocks) use 
rather device-based compatible (e.g. SoC-based compatible), instead of 
custom versioning of that component. For example use 
"vendor,soc1234-i2c" instead of "vendor,i2c-v2"." (Ref: 
https://elixir.bootlin.com/linux/v6.15.3/source/Documentation/devicetree/bindings/writing-bindings.rst#L79) 
# We need to add the full SoC name instead of versioning. e.g. 
compatible should contain full SoC name ax3000. Another example, we have 
seen is the designware I2C IP is used by MSCC, ocelot chipset. It is 
showing as below in the following: 
(https://elixir.bootlin.com/linux/v6.16-rc3/source/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml)

i2c@100400 { compatible = "mscc,ocelot-i2c 
<https://elixir.bootlin.com/linux/v6.16-rc3/B/ident/mscc%2Cocelot-i2c>", 
"snps,designware-i2c 
<https://elixir.bootlin.com/linux/v6.16-rc3/B/ident/snps%2Cdesignware-i2c>"; 
reg = <0x100400 0x100>, <0x198 0x8>; pinctrl-0 = <&i2c_pins>; 
pinctrl-names = "default"; interrupts = <8>; clocks = <&ahb_clk>; }; # 
We will add this compatible in the existing driver 
(drivers/tty/serial/xilinx_uartps.c) & bindings 
(Documentation/devicetree/bindings/serial/cdns,uart.yaml) since the IP 
is common. As per the above examples, I see two types of bindings. 
compatible = "axiado,ax3000-uart", "cdns,uart-r1p12" OR compatible = 
"axiado,ax3000-uart"Can you please help for this option? Apologies for 
the long thread again. Regards, Harshit.

On 6/23/2025 11:45 PM, Krzysztof Kozlowski wrote:
> CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
>
>
> On 23/06/2025 19:28, Harshit Shah wrote:
>> +     memory@0 {
>> +             device_type = "memory";
>> +             /* Cortex-A53 will use following memory map */
>> +             reg = <0x00000000 0x3D000000 0x00000000 0x23000000>,
> Lowercase hex, see DTS coding style.

I missed it. I will update it to lower case.


>
>> +     cpus {
>> +             #address-cells = <2>;
>> +             #size-cells = <0>;
>> +
>> +             cpu0: cpu@0 {
>> +                     device_type = "cpu";
>> +                     compatible = "arm,cortex-a53";
>> +                     reg = <0x0 0x0>;
>> +                     enable-method = "spin-table";
>> +                     cpu-release-addr = <0x0 0x3c0013a0>;
>> +                     d-cache-size = <0x8000>;
>> +                     d-cache-line-size = <64>;
>> +                     d-cache-sets = <128>;
>> +                     i-cache-size = <0x8000>;
>> +                     i-cache-line-size = <64>;
>> +                     i-cache-sets = <256>;
>> +                     next-level-cache = <&l2>;
>> +             };
> Missing blank line between each new node. See DTS coding style.

Noted, I will update between each nodes.


>
>> +             cpu1: cpu@1 {
>> +                     device_type = "cpu";
>> +                     compatible = "arm,cortex-a53";
>> +                     reg = <0x0 0x1>;
>> +                     enable-method = "spin-table";
>> +                     cpu-release-addr = <0x0 0x3c0013a0>;
>> +                     d-cache-size = <0x8000>;
>> +                     d-cache-line-size = <64>;
>> +                     d-cache-sets = <128>;
>> +                     i-cache-size = <0x8000>;
>> +                     i-cache-line-size = <64>;
>> +                     i-cache-sets = <256>;
>> +                     next-level-cache = <&l2>;
>> +             };
>> +             cpu2: cpu@2 {
>> +                     device_type = "cpu";
>> +                     compatible = "arm,cortex-a53";
>> +                     reg = <0x0 0x2>;
>> +                     enable-method = "spin-table";
>> +                     cpu-release-addr = <0x0 0x3c0013a0>;
>> +                     d-cache-size = <0x8000>;
>> +                     d-cache-line-size = <64>;
>> +                     d-cache-sets = <128>;
>> +                     i-cache-size = <0x8000>;
>> +                     i-cache-line-size = <64>;
>> +                     i-cache-sets = <256>;
>> +                     next-level-cache = <&l2>;
>> +             };
>> +             cpu3: cpu@3 {
>> +                     device_type = "cpu";
>> +                     compatible = "arm,cortex-a53";
>> +                     reg = <0x0 0x3>;
>> +                     enable-method = "spin-table";
>> +                     cpu-release-addr = <0x0 0x3c0013a0>;
>> +                     d-cache-size = <0x8000>;
>> +                     d-cache-line-size = <64>;
>> +                     d-cache-sets = <128>;
>> +                     i-cache-size = <0x8000>;
>> +                     i-cache-line-size = <64>;
>> +                     i-cache-sets = <256>;
>> +                     next-level-cache = <&l2>;
>> +             };
>> +             l2: l2-cache0 {
>> +                     compatible = "cache";
>> +                     cache-size = <0x100000>;
>> +                     cache-unified;
>> +                     cache-line-size = <64>;
>> +                     cache-sets = <1024>;
>> +                     cache-level = <2>;
>> +             };
>> +     };
>> +
>> +     clocks {
>> +             clk_xin: clock-200000000 {
>> +                     compatible = "fixed-clock";
>> +                     #clock-cells = <0>;
>> +                     clock-frequency = <200000000>;
>> +                     clock-output-names = "clk_xin";
>> +             };
>> +             refclk: clock-125000000 {
>> +                     compatible = "fixed-clock";
>> +                     #clock-cells = <0>;
>> +                     clock-frequency = <125000000>;
>> +             };
>> +     };
>> +
>> +     soc {
>> +             compatible = "simple-bus";
>> +             ranges;
>> +             #address-cells = <2>;
>> +             #size-cells = <2>;
>> +             interrupt-parent = <&gic500>;
>> +
>> +             gic500: interrupt-controller@80300000 {
>> +                     compatible = "arm,gic-v3";
>> +                     reg = <0x00 0x80300000 0x00 0x10000>,
>> +                               <0x00 0x80380000 0x00 0x80000>;
> Does not look aligned.

Agreed. I will update the alignment.


>
>> +                     ranges;
>> +                     #interrupt-cells = <3>;
>> +                     #address-cells = <2>;
>> +                     #size-cells = <2>;
>> +                     interrupt-controller;
>> +                     #redistributor-regions = <1>;
>> +                     interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> +             };
>> +
>> +             /* GPIO Controller banks 0 - 7 */
>> +             gpio0: gpio-controller@80500000 {
>> +                     compatible = "cdns,gpio-r1p02";
>> +                     reg = <0x00 0x80500000 0x00  0x400>;
> Only one space, not double space.

Agreed. There is double space in every GPIO nodes, I will update the same.


Regards,

Harshit.