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X-OriginatorOrg: axiado.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jun 2025 17:28:40.0247 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 724dce83-e04d-46d5-1293-08ddb27b65b2 X-MS-Exchange-CrossTenant-Id: ff2db17c-4338-408e-9036-2dee8e3e17d7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=ff2db17c-4338-408e-9036-2dee8e3e17d7;Ip=[50.233.182.194];Helo=[[127.0.0.1]] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00029928.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR18MB5080 Add initial device tree support for the AX3000 SoC and its evaluation platform. The AX3000 is a multi-core SoC featuring 4 Cortex-A53 cores, Secure Vault, AI Engine and Firewall. This commit adds support for Cortex-A53 CPUs, timer, UARTs, and I3C controllers on the AX3000 evaluation board. Signed-off-by: Harshit Shah --- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/axiado/Makefile | 2 + arch/arm64/boot/dts/axiado/ax3000-evk.dts | 79 +++++ arch/arm64/boot/dts/axiado/ax3000.dtsi | 488 ++++++++++++++++++++++++++= ++++ 4 files changed, 570 insertions(+) diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 79b73a21ddc22b17308554e502f8207392935b45..47dd8a1a7960d179ee28969a1d6= 750bfa0d73da1 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -9,6 +9,7 @@ subdir-y +=3D amlogic subdir-y +=3D apm subdir-y +=3D apple subdir-y +=3D arm +subdir-y +=3D axiado subdir-y +=3D bitmain subdir-y +=3D blaize subdir-y +=3D broadcom diff --git a/arch/arm64/boot/dts/axiado/Makefile b/arch/arm64/boot/dts/axia= do/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..6676ad07db6129f8b333b0feffe= e705d272517c2 --- /dev/null +++ b/arch/arm64/boot/dts/axiado/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_AXIADO) +=3D ax3000-evk.dtb diff --git a/arch/arm64/boot/dts/axiado/ax3000-evk.dts b/arch/arm64/boot/dt= s/axiado/ax3000-evk.dts new file mode 100644 index 0000000000000000000000000000000000000000..cc3bcf681c32430d251f20f6d52= 905423c182f3b --- /dev/null +++ b/arch/arm64/boot/dts/axiado/ax3000-evk.dts @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2021-25 Axiado Corporation (or its affiliates). All right= s reserved. + */ + +/dts-v1/; + +#include "ax3000.dtsi" + +/ { + model =3D "Axiado AX3000 EVK"; + compatible =3D "axiado,ax3000-evk", "axiado,ax3000"; + #address-cells =3D <2>; + #size-cells =3D <2>; + + aliases { + serial3 =3D &uart3; + }; + + chosen { + stdout-path =3D "serial3:115200"; + }; + + memory@0 { + device_type =3D "memory"; + /* Cortex-A53 will use following memory map */ + reg =3D <0x00000000 0x3D000000 0x00000000 0x23000000>, + <0x00000004 0x00000000 0x00000000 0x80000000>; + }; +}; + +/* GPIO bank 0 - 7 */ +&gpio0 { + status =3D "okay"; +}; + +&gpio1 { + status =3D "okay"; +}; + +&gpio2 { + status =3D "okay"; +}; + +&gpio3 { + status =3D "okay"; +}; + +&gpio4 { + status =3D "okay"; +}; + +&gpio5 { + status =3D "okay"; +}; + +&gpio6 { + status =3D "okay"; +}; + +&gpio7 { + status =3D "okay"; +}; + +&uart0 { + status =3D "okay"; +}; + +&uart1 { + status =3D "okay"; +}; + +&uart2 { + status =3D "okay"; +}; + +&uart3 { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/axiado/ax3000.dtsi b/arch/arm64/boot/dts/a= xiado/ax3000.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..ea85ae8ca5dea5ab3288a2770b1= 8d7aeb66cad03 --- /dev/null +++ b/arch/arm64/boot/dts/axiado/ax3000.dtsi @@ -0,0 +1,488 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2021-25=C2=A0Axiado Corporation (or its affiliates). All = rights reserved. + */ + +/dts-v1/; + +#include +#include + +/memreserve/ 0x3c0013a0 0x00000008; /* cpu-release-addr */ +/ { + model =3D "Axiado AX3000"; + interrupt-parent =3D <&gic500>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x0 0x0>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0x0 0x3c0013a0>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + next-level-cache =3D <&l2>; + }; + cpu1: cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x0 0x1>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0x0 0x3c0013a0>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + next-level-cache =3D <&l2>; + }; + cpu2: cpu@2 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x0 0x2>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0x0 0x3c0013a0>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + next-level-cache =3D <&l2>; + }; + cpu3: cpu@3 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x0 0x3>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0x0 0x3c0013a0>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + next-level-cache =3D <&l2>; + }; + l2: l2-cache0 { + compatible =3D "cache"; + cache-size =3D <0x100000>; + cache-unified; + cache-line-size =3D <64>; + cache-sets =3D <1024>; + cache-level =3D <2>; + }; + }; + + clocks { + clk_xin: clock-200000000 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <200000000>; + clock-output-names =3D "clk_xin"; + }; + refclk: clock-125000000 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <125000000>; + }; + }; + + soc { + compatible =3D "simple-bus"; + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-parent =3D <&gic500>; + + gic500: interrupt-controller@80300000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x00 0x80300000 0x00 0x10000>, + <0x00 0x80380000 0x00 0x80000>; + ranges; + #interrupt-cells =3D <3>; + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-controller; + #redistributor-regions =3D <1>; + interrupts =3D ; + }; + + /* GPIO Controller banks 0 - 7 */ + gpio0: gpio-controller@80500000 { + compatible =3D "cdns,gpio-r1p02"; + reg =3D <0x00 0x80500000 0x00 0x400>; + clocks =3D <&refclk>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + status =3D "disabled"; + }; + gpio1: gpio-controller@80580000 { + compatible =3D "cdns,gpio-r1p02"; + reg =3D <0x00 0x80580000 0x00 0x400>; + clocks =3D <&refclk>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + status =3D "disabled"; + }; + gpio2: gpio-controller@80600000 { + compatible =3D "cdns,gpio-r1p02"; + reg =3D <0x00 0x80600000 0x00 0x400>; + clocks =3D <&refclk>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + status =3D "disabled"; + }; + gpio3: gpio-controller@80680000 { + compatible =3D "cdns,gpio-r1p02"; + reg =3D <0x00 0x80680000 0x00 0x400>; + clocks =3D <&refclk>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + status =3D "disabled"; + }; + gpio4: gpio-controller@80700000 { + compatible =3D "cdns,gpio-r1p02"; + reg =3D <0x00 0x80700000 0x00 0x400>; + clocks =3D <&refclk>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + status =3D "disabled"; + }; + gpio5: gpio-controller@80780000 { + compatible =3D "cdns,gpio-r1p02"; + reg =3D <0x00 0x80780000 0x00 0x400>; + clocks =3D <&refclk>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + status =3D "disabled"; + }; + gpio6: gpio-controller@80800000 { + compatible =3D "cdns,gpio-r1p02"; + reg =3D <0x00 0x80800000 0x00 0x400>; + clocks =3D <&refclk>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + status =3D "disabled"; + }; + gpio7: gpio-controller@80880000 { + compatible =3D "cdns,gpio-r1p02"; + reg =3D <0x00 0x80880000 0x00 0x400>; + clocks =3D <&refclk>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + status =3D "disabled"; + }; + + /* I3C Controller 0 - 16 */ + i3c0: i3c@80500400 { + compatible =3D "cdns,i3c-master"; + reg =3D <0x00 0x80500400 0x00 0x400>; + clocks =3D <&refclk &clk_xin>; + clock-names =3D "pclk", "sysclk"; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + i2c-scl-hz =3D <100000>; + i3c-scl-hz =3D <400000>; + #address-cells =3D <3>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + i3c1: i3c@80500800 { + compatible =3D "cdns,i3c-master"; + reg =3D <0x00 0x80500800 0x00 0x400>; + clocks =3D <&refclk &clk_xin>; + clock-names =3D "pclk", "sysclk"; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + i2c-scl-hz =3D <100000>; + i3c-scl-hz =3D <400000>; + #address-cells =3D <3>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + i3c2: i3c@80580400 { + compatible =3D "cdns,i3c-master"; + reg =3D <0x00 0x80580400 0x00 0x400>; + clocks =3D <&refclk &clk_xin>; + clock-names =3D "pclk", "sysclk"; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + i2c-scl-hz =3D <100000>; + i3c-scl-hz =3D <400000>; + #address-cells =3D <3>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + i3c3: i3c@80580800 { + compatible =3D "cdns,i3c-master"; + reg =3D <0x00 0x80580800 0x00 0x400>; + clocks =3D <&refclk &clk_xin>; + clock-names =3D "pclk", "sysclk"; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + i2c-scl-hz =3D <100000>; + i3c-scl-hz =3D <400000>; + #address-cells =3D <3>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + i3c4: i3c@80600400 { + compatible =3D "cdns,i3c-master"; + reg =3D <0x00 0x80600400 0x00 0x400>; + clocks =3D <&refclk &clk_xin>; + clock-names =3D "pclk", "sysclk"; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + i2c-scl-hz =3D <100000>; + i3c-scl-hz =3D <400000>; + #address-cells =3D <3>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + i3c5: i3c@80600800 { + compatible =3D "cdns,i3c-master"; + reg =3D <0x00 0x80600800 0x00 0x400>; + clocks =3D <&refclk &clk_xin>; + clock-names =3D "pclk", "sysclk"; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + i2c-scl-hz =3D <100000>; + i3c-scl-hz =3D <400000>; + #address-cells =3D <3>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + i3c6: i3c@80680400 { + compatible =3D "cdns,i3c-master"; + reg =3D <0x00 0x80680400 0x00 0x400>; + clocks =3D <&refclk &clk_xin>; + clock-names =3D "pclk", "sysclk"; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + i2c-scl-hz =3D <100000>; + i3c-scl-hz =3D <400000>; + #address-cells =3D <3>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + i3c7: i3c@80680800 { + compatible =3D "cdns,i3c-master"; + reg =3D <0x00 0x80680800 0x00 0x400>; + clocks =3D <&refclk &clk_xin>; + clock-names =3D "pclk", "sysclk"; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + i2c-scl-hz =3D <100000>; + i3c-scl-hz =3D <400000>; + #address-cells =3D <3>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + i3c8: i3c@80700400 { + compatible =3D "cdns,i3c-master"; + reg =3D <0x00 0x80700400 0x00 0x400>; + clocks =3D <&refclk &clk_xin>; + clock-names =3D "pclk", "sysclk"; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + i2c-scl-hz =3D <100000>; + i3c-scl-hz =3D <400000>; + #address-cells =3D <3>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + i3c9: i3c@80700800 { + compatible =3D "cdns,i3c-master"; + reg =3D <0x00 0x80700800 0x00 0x400>; + clocks =3D <&refclk &clk_xin>; + clock-names =3D "pclk", "sysclk"; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + i2c-scl-hz =3D <100000>; + i3c-scl-hz =3D <400000>; + #address-cells =3D <3>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + i3c10: i3c@80780400 { + compatible =3D "cdns,i3c-master"; + reg =3D <0x00 0x80780400 0x00 0x400>; + clocks =3D <&refclk &clk_xin>; + clock-names =3D "pclk", "sysclk"; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + i2c-scl-hz =3D <100000>; + i3c-scl-hz =3D <400000>; + #address-cells =3D <3>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + i3c11: i3c@80780800 { + compatible =3D "cdns,i3c-master"; + reg =3D <0x00 0x80780800 0x00 0x400>; + clocks =3D <&refclk &clk_xin>; + clock-names =3D "pclk", "sysclk"; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + i2c-scl-hz =3D <100000>; + i3c-scl-hz =3D <400000>; + #address-cells =3D <3>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + i3c12: i3c@80800400 { + compatible =3D "cdns,i3c-master"; + reg =3D <0x00 0x80800400 0x00 0x400>; + clocks =3D <&refclk &clk_xin>; + clock-names =3D "pclk", "sysclk"; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + i2c-scl-hz =3D <100000>; + i3c-scl-hz =3D <400000>; + #address-cells =3D <3>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + i3c13: i3c@80800800 { + compatible =3D "cdns,i3c-master"; + reg =3D <0x00 0x80800800 0x00 0x400>; + clocks =3D <&refclk &clk_xin>; + clock-names =3D "pclk", "sysclk"; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + i2c-scl-hz =3D <100000>; + i3c-scl-hz =3D <400000>; + #address-cells =3D <3>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + i3c14: i3c@80880400 { + compatible =3D "cdns,i3c-master"; + reg =3D <0x00 0x80880400 0x00 0x400>; + clocks =3D <&refclk &clk_xin>; + clock-names =3D "pclk", "sysclk"; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + i2c-scl-hz =3D <100000>; + i3c-scl-hz =3D <400000>; + #address-cells =3D <3>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + i3c15: i3c@80880800 { + compatible =3D "cdns,i3c-master"; + reg =3D <0x00 0x80880800 0x00 0x400>; + clocks =3D <&refclk &clk_xin>; + clock-names =3D "pclk", "sysclk"; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + i2c-scl-hz =3D <100000>; + i3c-scl-hz =3D <400000>; + #address-cells =3D <3>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + i3c16: i3c@80620400 { + compatible =3D "cdns,i3c-master"; + reg =3D <0x00 0x80620400 0x00 0x400>; + clocks =3D <&refclk &clk_xin>; + clock-names =3D "pclk", "sysclk"; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + i2c-scl-hz =3D <100000>; + i3c-scl-hz =3D <400000>; + #address-cells =3D <3>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + uart0: serial@80520000 { + compatible =3D "xlnx,zynqmp-uart", "cdns,uart-r1p12"; + reg =3D <0x00 0x80520000 0x00 0x100>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + clock-names =3D "uart_clk", "pclk"; + clocks =3D <&refclk &refclk>; + status =3D "disabled"; + }; + uart1: serial@805a0000 { + compatible =3D "xlnx,zynqmp-uart", "cdns,uart-r1p12"; + reg =3D <0x00 0x805A0000 0x00 0x100>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + clock-names =3D "uart_clk", "pclk"; + clocks =3D <&refclk &refclk>; + status =3D "disabled"; + }; + uart2: serial@80620000 { + compatible =3D "xlnx,zynqmp-uart", "cdns,uart-r1p12"; + reg =3D <0x00 0x80620000 0x00 0x100>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + clock-names =3D "uart_clk", "pclk"; + clocks =3D <&refclk &refclk>; + status =3D "disabled"; + }; + uart3: serial@80520800 { + compatible =3D "xlnx,zynqmp-uart", "cdns,uart-r1p12"; + reg =3D <0x00 0x80520800 0x00 0x100>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + clock-names =3D "uart_clk", "pclk"; + clocks =3D <&refclk &refclk>; + status =3D "disabled"; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupt-parent =3D <&gic500>; + interrupts =3D , + , + , + ; + }; +}; --=20 2.25.1