[PATCH v2 3/4] clk: renesas: r9a09g077-cpg: Add PCLKL core clock

Prabhakar posted 4 patches 3 months, 3 weeks ago
[PATCH v2 3/4] clk: renesas: r9a09g077-cpg: Add PCLKL core clock
Posted by Prabhakar 3 months, 3 weeks ago
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add the Peripheral Module Clock L (PCLKL) for the RZ/T2H (R9A09G077) SoC.
PCLKL is sourced from PLL1 and runs at 62.5MHz. It is used by various
low-speed peripherals such as IIC and WDT.

Also update LAST_DT_CORE_CLK to reflect the addition of PCLKL, ensuring
correct enumeration of core clocks exposed to the DT.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2:
- New patch to add PCLKL core clock.
---
 drivers/clk/renesas/r9a09g077-cpg.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/renesas/r9a09g077-cpg.c b/drivers/clk/renesas/r9a09g077-cpg.c
index 206816a2df23..b83ef933ae0f 100644
--- a/drivers/clk/renesas/r9a09g077-cpg.c
+++ b/drivers/clk/renesas/r9a09g077-cpg.c
@@ -66,7 +66,7 @@ enum rzt2h_clk_types {
 
 enum clk_ids {
 	/* Core Clock Outputs exported to DT */
-	LAST_DT_CORE_CLK = R9A09G077_CLK_PCLKM,
+	LAST_DT_CORE_CLK = R9A09G077_CLK_PCLKL,
 
 	/* External Input Clocks */
 	CLK_EXTAL,
@@ -140,6 +140,7 @@ static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = {
 		dtable_1_2),
 	DEF_FIXED("PCLKGPTL", R9A09G077_CLK_PCLKGPTL, CLK_SEL_CLK_PLL1, 2, 1),
 	DEF_FIXED("PCLKM", R9A09G077_CLK_PCLKM, CLK_SEL_CLK_PLL1, 8, 1),
+	DEF_FIXED("PCLKL", R9A09G077_CLK_PCLKL, CLK_SEL_CLK_PLL1, 16, 1),
 };
 
 static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst = {
-- 
2.49.0
Re: [PATCH v2 3/4] clk: renesas: r9a09g077-cpg: Add PCLKL core clock
Posted by Geert Uytterhoeven 3 months, 3 weeks ago
On Tue, 17 Jun 2025 at 17:58, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add the Peripheral Module Clock L (PCLKL) for the RZ/T2H (R9A09G077) SoC.
> PCLKL is sourced from PLL1 and runs at 62.5MHz. It is used by various
> low-speed peripherals such as IIC and WDT.
>
> Also update LAST_DT_CORE_CLK to reflect the addition of PCLKL, ensuring
> correct enumeration of core clocks exposed to the DT.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v1->v2:
> - New patch to add PCLKL core clock.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk for v6.17.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds