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Tue, 17 Jun 2025 08:58:02 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:a081:30f1:e1c7:6f28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a568a53f79sm14189115f8f.4.2025.06.17.08.58.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Jun 2025 08:58:01 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 3/4] clk: renesas: r9a09g077-cpg: Add PCLKL core clock Date: Tue, 17 Jun 2025 16:57:56 +0100 Message-ID: <20250617155757.149597-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250617155757.149597-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250617155757.149597-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add the Peripheral Module Clock L (PCLKL) for the RZ/T2H (R9A09G077) SoC. PCLKL is sourced from PLL1 and runs at 62.5MHz. It is used by various low-speed peripherals such as IIC and WDT. Also update LAST_DT_CORE_CLK to reflect the addition of PCLKL, ensuring correct enumeration of core clocks exposed to the DT. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v1->v2: - New patch to add PCLKL core clock. --- drivers/clk/renesas/r9a09g077-cpg.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/renesas/r9a09g077-cpg.c b/drivers/clk/renesas/r9a0= 9g077-cpg.c index 206816a2df23..b83ef933ae0f 100644 --- a/drivers/clk/renesas/r9a09g077-cpg.c +++ b/drivers/clk/renesas/r9a09g077-cpg.c @@ -66,7 +66,7 @@ enum rzt2h_clk_types { =20 enum clk_ids { /* Core Clock Outputs exported to DT */ - LAST_DT_CORE_CLK =3D R9A09G077_CLK_PCLKM, + LAST_DT_CORE_CLK =3D R9A09G077_CLK_PCLKL, =20 /* External Input Clocks */ CLK_EXTAL, @@ -140,6 +140,7 @@ static const struct cpg_core_clk r9a09g077_core_clks[] = __initconst =3D { dtable_1_2), DEF_FIXED("PCLKGPTL", R9A09G077_CLK_PCLKGPTL, CLK_SEL_CLK_PLL1, 2, 1), DEF_FIXED("PCLKM", R9A09G077_CLK_PCLKM, CLK_SEL_CLK_PLL1, 8, 1), + DEF_FIXED("PCLKL", R9A09G077_CLK_PCLKL, CLK_SEL_CLK_PLL1, 16, 1), }; =20 static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst =3D { --=20 2.49.0