.../bindings/clock/qcom,sa8775p-camcc.yaml | 15 ++++ .../bindings/clock/qcom,sm8450-camcc.yaml | 20 +++-- .../bindings/clock/qcom,sm8450-videocc.yaml | 18 +++-- arch/arm64/boot/dts/qcom/sm8450.dtsi | 12 ++- arch/arm64/boot/dts/qcom/sm8550.dtsi | 12 ++- arch/arm64/boot/dts/qcom/sm8650.dtsi | 6 +- drivers/clk/qcom/camcc-sm8450.c | 89 +++++++++++----------- drivers/clk/qcom/camcc-sm8550.c | 85 +++++++++++---------- drivers/clk/qcom/camcc-sm8650.c | 83 ++++++++++---------- drivers/clk/qcom/camcc-x1e80100.c | 67 ++++++++-------- drivers/clk/qcom/clk-alpha-pll.c | 57 ++++++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 3 + drivers/clk/qcom/common.c | 81 +++++++++++++++++--- drivers/clk/qcom/common.h | 10 +++ drivers/clk/qcom/videocc-sm8450.c | 58 ++++++-------- drivers/clk/qcom/videocc-sm8550.c | 66 ++++++++-------- 16 files changed, 421 insertions(+), 261 deletions(-)
In recent QCOM chipsets, PLLs require more than one power domain to be
kept ON to configure the PLL. But the current code doesn't enable all
the required power domains while configuring the PLLs, this leads to
functional issues due to suboptimal settings of PLLs.
To address this, add support for handling runtime power management,
configuring plls and enabling critical clocks from qcom_cc_really_probe.
The clock controller can specify PLLs, critical clocks, and runtime PM
requirements using the descriptor data. The code in qcom_cc_really_probe()
ensures all necessary power domains are enabled before configuring PLLs
or critical clocks.
This series fixes the below warning reported in SM8550 venus testing due
to video_cc_pll0 not properly getting configured during videocc probe
[ 46.535132] Lucid PLL latch failed. Output may be unstable!
The patch adding support to configure the PLLs from common code is
picked from below series and updated it.
https://lore.kernel.org/all/20250113-support-pll-reconfigure-v1-0-1fae6bc1062d@quicinc.com/
This series is dependent on bindings patch in below Vladimir's series, hence
included the Vladimir's series patches also in this series and updated them.
https://lore.kernel.org/all/20250303225521.1780611-1-vladimir.zapolskiy@linaro.org/
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
---
Changes in v5:
- Reversed order of patches 2 & 3 to add MXC support in SM8450
camcc bindings first and then moved SC8280XP camcc to SA8775P
camcc to have single power domain support for it.
- Added return code for qcom_cc_clk_pll_configure() and
returned -EINVAL in case if PLL config or registers is
NULL in patch 6 [Bryan]
- Added separate CBCR's list for SM8650 videocc and
updated clk_cbcrs list based on compatible in patch 8[Konrad]
- Added R-By tags received on v4
- Link to v4: https://lore.kernel.org/r/20250515-videocc-pll-multi-pd-voting-v4-0-571c63297d01@quicinc.com
Changes in v4:
- Updated the SC8280XP camcc bindings patch to fix the
required-opps warning reported by kernel bot
- Updated the description of power-domains, required-opps of SM8450 camcc
bindings as per review comments on v3 [Bryan]
- Moved the PLL config checks to calling function code [Dmitry]
- Removed qcom_clk_reg_setting struct and regmap_update_bits() code.
Added a .clk_regs_configure() callback that clock drivers can implement
if they require to update some misc register settings [Dmitry]
- Moved the PLLs and CBCRs data to a separate qcom_cc_driver_data
struct to avoid bloating up the CC descriptor structure
- Updated the videocc and camcc driver patches to incorporate above
qcom_cc_driver_data change
- Updated the commit text of DT patches [Bryan]
- Added the R-By, T-By tags received on v3
- Link to v3: https://lore.kernel.org/r/20250327-videocc-pll-multi-pd-voting-v3-0-895fafd62627@quicinc.com
Changes in v3:
- Updated the videocc bindings patch to add required-opps for MXC power domain [Dmitry]
and added Bryan & Rob R/A-By tags received for this patch on v1.
- Included the Vladimir's bindings patch for SM8450 camcc bindings to
add multiple PD support and updated them to fix the bot warnings.
- Moved SC8280XP camcc bindings to SA8775P camcc since SC8280XP only
require single MMCX power domain
- Split runtime PM and PLL configuration to separate patches [Dmitry]
- Removed direct regmap_update_bits to configure clock CBCR's and
using clock helpers to configure the CBCR registers [Dmitry, Bryan]
- Added new helpers to configure all PLLs & update misc clock
register settings from common code [Dmitry, Bryan]
- Updated the name of qcom_clk_cfg structure to qcom_clk_reg_setting [Konrad]
- Updated the fields in structure from unsigned int to u32 and added
val field to this structure [Konrad]
- Added a new u32 array for cbcr branch clocks & num_clk_cbcrs fields
to maintain the list of critical clock cbcrs in clock controller
descriptor [Konrad]
- Updated the plls field to alpha_plls in descriptor structure [Konrad]
- Added WARN() in PLL configure function if PLL type passed is not
supported. The suggestion is to use BUG(), but updated it to
WARN() to avoid checkpatch warning. [Bjorn]
- Moved the pll configure and helper macros to PLL code from common code [Bjorn]
- Updated camcc drivers for SM8450, SM8550, SM8650 and X1E80100 targets
with support to configure PLLs from common code and added MXC power
domain in corresponding camcc DT nodes. [Bryan]
- Added Dmitry and Bryan R-By tags received on videocc DT node changes in v1
- Link to v2: https://lore.kernel.org/r/20250306-videocc-pll-multi-pd-voting-v2-0-0cd00612bc0e@quicinc.com
Changes in v2:
- Added support to handle rpm, PLL configuration and enable critical
clocks from qcom_cc_really_probe() in common code as per v1 commments
from Bryan, Konrad and Dmitry
- Added patches to configure PLLs from common code
- Updated the SM8450, SM8550 videocc patches to use the newly
added support to handle rpm, configure PLLs from common code
- Split the DT change for each target separately as per
Dmitry comments
- Added R-By and A-By tags received on v1
- Link to v1: https://lore.kernel.org/r/20250218-videocc-pll-multi-pd-voting-v1-0-cfe6289ea29b@quicinc.com
---
Jagadeesh Kona (15):
dt-bindings: clock: qcom,sm8450-videocc: Add MXC power domain
dt-bindings: clock: qcom,sm8450-camcc: Move sc8280xp camcc to sa8775p camcc
clk: qcom: common: Handle runtime power management in qcom_cc_really_probe
clk: qcom: common: Add support to configure clk regs in qcom_cc_really_probe
clk: qcom: videocc-sm8450: Move PLL & clk configuration to really probe
clk: qcom: videocc-sm8550: Move PLL & clk configuration to really probe
clk: qcom: camcc-sm8450: Move PLL & clk configuration to really probe
clk: qcom: camcc-sm8550: Move PLL & clk configuration to really probe
clk: qcom: camcc-sm8650: Move PLL & clk configuration to really probe
clk: qcom: camcc-x1e80100: Move PLL & clk configuration to really probe
arm64: dts: qcom: sm8450: Additionally manage MXC power domain in videocc
arm64: dts: qcom: sm8550: Additionally manage MXC power domain in videocc
arm64: dts: qcom: sm8650: Additionally manage MXC power domain in videocc
arm64: dts: qcom: sm8450: Additionally manage MXC power domain in camcc
arm64: dts: qcom: sm8650: Additionally manage MXC power domain in camcc
Taniya Das (1):
clk: qcom: clk-alpha-pll: Add support for common PLL configuration function
Vladimir Zapolskiy (2):
dt-bindings: clock: qcom,sm8450-camcc: Allow to specify two power domains
arm64: dts: qcom: sm8550: Additionally manage MXC power domain in camcc
.../bindings/clock/qcom,sa8775p-camcc.yaml | 15 ++++
.../bindings/clock/qcom,sm8450-camcc.yaml | 20 +++--
.../bindings/clock/qcom,sm8450-videocc.yaml | 18 +++--
arch/arm64/boot/dts/qcom/sm8450.dtsi | 12 ++-
arch/arm64/boot/dts/qcom/sm8550.dtsi | 12 ++-
arch/arm64/boot/dts/qcom/sm8650.dtsi | 6 +-
drivers/clk/qcom/camcc-sm8450.c | 89 +++++++++++-----------
drivers/clk/qcom/camcc-sm8550.c | 85 +++++++++++----------
drivers/clk/qcom/camcc-sm8650.c | 83 ++++++++++----------
drivers/clk/qcom/camcc-x1e80100.c | 67 ++++++++--------
drivers/clk/qcom/clk-alpha-pll.c | 57 ++++++++++++++
drivers/clk/qcom/clk-alpha-pll.h | 3 +
drivers/clk/qcom/common.c | 81 +++++++++++++++++---
drivers/clk/qcom/common.h | 10 +++
drivers/clk/qcom/videocc-sm8450.c | 58 ++++++--------
drivers/clk/qcom/videocc-sm8550.c | 66 ++++++++--------
16 files changed, 421 insertions(+), 261 deletions(-)
---
base-commit: 138cfc44b3c4a5fb800388c6e27be169970fb9f7
change-id: 20250218-videocc-pll-multi-pd-voting-d614dce910e7
Best regards,
--
Jagadeesh Kona <quic_jkona@quicinc.com>
Hi, On 30/05/2025 15:20, Jagadeesh Kona wrote: > In recent QCOM chipsets, PLLs require more than one power domain to be > kept ON to configure the PLL. But the current code doesn't enable all > the required power domains while configuring the PLLs, this leads to > functional issues due to suboptimal settings of PLLs. > > To address this, add support for handling runtime power management, > configuring plls and enabling critical clocks from qcom_cc_really_probe. > The clock controller can specify PLLs, critical clocks, and runtime PM > requirements using the descriptor data. The code in qcom_cc_really_probe() > ensures all necessary power domains are enabled before configuring PLLs > or critical clocks. > > This series fixes the below warning reported in SM8550 venus testing due > to video_cc_pll0 not properly getting configured during videocc probe > > [ 46.535132] Lucid PLL latch failed. Output may be unstable! > > The patch adding support to configure the PLLs from common code is > picked from below series and updated it. > https://lore.kernel.org/all/20250113-support-pll-reconfigure-v1-0-1fae6bc1062d@quicinc.com/ > > This series is dependent on bindings patch in below Vladimir's series, hence > included the Vladimir's series patches also in this series and updated them. > https://lore.kernel.org/all/20250303225521.1780611-1-vladimir.zapolskiy@linaro.org/ Could you re-spin patches 13 to 18 to fix the bindings checks ? Thanks, Neil <snip>
On 7/29/2025 8:19 PM, neil.armstrong@linaro.org wrote: > Hi, > > On 30/05/2025 15:20, Jagadeesh Kona wrote: >> In recent QCOM chipsets, PLLs require more than one power domain to be >> kept ON to configure the PLL. But the current code doesn't enable all >> the required power domains while configuring the PLLs, this leads to >> functional issues due to suboptimal settings of PLLs. >> >> To address this, add support for handling runtime power management, >> configuring plls and enabling critical clocks from qcom_cc_really_probe. >> The clock controller can specify PLLs, critical clocks, and runtime PM >> requirements using the descriptor data. The code in qcom_cc_really_probe() >> ensures all necessary power domains are enabled before configuring PLLs >> or critical clocks. >> >> This series fixes the below warning reported in SM8550 venus testing due >> to video_cc_pll0 not properly getting configured during videocc probe >> >> [ 46.535132] Lucid PLL latch failed. Output may be unstable! >> >> The patch adding support to configure the PLLs from common code is >> picked from below series and updated it. >> https://lore.kernel.org/all/20250113-support-pll-reconfigure-v1-0-1fae6bc1062d@quicinc.com/ >> >> This series is dependent on bindings patch in below Vladimir's series, hence >> included the Vladimir's series patches also in this series and updated them. >> https://lore.kernel.org/all/20250303225521.1780611-1-vladimir.zapolskiy@linaro.org/ > > > Could you re-spin patches 13 to 18 to fix the bindings checks ? > I tried applying the patches 13-18 on latest linux-next tip and I see they are applied properly without any conflicts. Bjorn, can you please help to pick the patches 13-18 to fix the bindings checks[1]. Please let me know if anything needed from me. [1]: https://lore.kernel.org/oe-kbuild-all/453bd020-8124-4a7d-8d0f-8180d38f1ebc@quicinc.com/#t Thanks, Jagadeesh > Thanks, > Neil > > <snip> >
On 30/05/2025 14:20, Jagadeesh Kona wrote: > In recent QCOM chipsets, PLLs require more than one power domain to be > kept ON to configure the PLL. But the current code doesn't enable all > the required power domains while configuring the PLLs, this leads to > functional issues due to suboptimal settings of PLLs. > > To address this, add support for handling runtime power management, > configuring plls and enabling critical clocks from qcom_cc_really_probe. > The clock controller can specify PLLs, critical clocks, and runtime PM > requirements using the descriptor data. The code in qcom_cc_really_probe() > ensures all necessary power domains are enabled before configuring PLLs > or critical clocks. > > This series fixes the below warning reported in SM8550 venus testing due > to video_cc_pll0 not properly getting configured during videocc probe > > [ 46.535132] Lucid PLL latch failed. Output may be unstable! > > The patch adding support to configure the PLLs from common code is > picked from below series and updated it. > https://lore.kernel.org/all/20250113-support-pll-reconfigure-v1-0-1fae6bc1062d@quicinc.com/ > > This series is dependent on bindings patch in below Vladimir's series, hence > included the Vladimir's series patches also in this series and updated them. > https://lore.kernel.org/all/20250303225521.1780611-1-vladimir.zapolskiy@linaro.org/ > > Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> > --- > Changes in v5: > - Reversed order of patches 2 & 3 to add MXC support in SM8450 > camcc bindings first and then moved SC8280XP camcc to SA8775P > camcc to have single power domain support for it. > - Added return code for qcom_cc_clk_pll_configure() and > returned -EINVAL in case if PLL config or registers is > NULL in patch 6 [Bryan] > - Added separate CBCR's list for SM8650 videocc and > updated clk_cbcrs list based on compatible in patch 8[Konrad] > - Added R-By tags received on v4 > - Link to v4: https://lore.kernel.org/r/20250515-videocc-pll-multi-pd-voting-v4-0-571c63297d01@quicinc.com > > Changes in v4: > - Updated the SC8280XP camcc bindings patch to fix the > required-opps warning reported by kernel bot > - Updated the description of power-domains, required-opps of SM8450 camcc > bindings as per review comments on v3 [Bryan] > - Moved the PLL config checks to calling function code [Dmitry] > - Removed qcom_clk_reg_setting struct and regmap_update_bits() code. > Added a .clk_regs_configure() callback that clock drivers can implement > if they require to update some misc register settings [Dmitry] > - Moved the PLLs and CBCRs data to a separate qcom_cc_driver_data > struct to avoid bloating up the CC descriptor structure > - Updated the videocc and camcc driver patches to incorporate above > qcom_cc_driver_data change > - Updated the commit text of DT patches [Bryan] > - Added the R-By, T-By tags received on v3 > - Link to v3: https://lore.kernel.org/r/20250327-videocc-pll-multi-pd-voting-v3-0-895fafd62627@quicinc.com > > Changes in v3: > - Updated the videocc bindings patch to add required-opps for MXC power domain [Dmitry] > and added Bryan & Rob R/A-By tags received for this patch on v1. > - Included the Vladimir's bindings patch for SM8450 camcc bindings to > add multiple PD support and updated them to fix the bot warnings. > - Moved SC8280XP camcc bindings to SA8775P camcc since SC8280XP only > require single MMCX power domain > - Split runtime PM and PLL configuration to separate patches [Dmitry] > - Removed direct regmap_update_bits to configure clock CBCR's and > using clock helpers to configure the CBCR registers [Dmitry, Bryan] > - Added new helpers to configure all PLLs & update misc clock > register settings from common code [Dmitry, Bryan] > - Updated the name of qcom_clk_cfg structure to qcom_clk_reg_setting [Konrad] > - Updated the fields in structure from unsigned int to u32 and added > val field to this structure [Konrad] > - Added a new u32 array for cbcr branch clocks & num_clk_cbcrs fields > to maintain the list of critical clock cbcrs in clock controller > descriptor [Konrad] > - Updated the plls field to alpha_plls in descriptor structure [Konrad] > - Added WARN() in PLL configure function if PLL type passed is not > supported. The suggestion is to use BUG(), but updated it to > WARN() to avoid checkpatch warning. [Bjorn] > - Moved the pll configure and helper macros to PLL code from common code [Bjorn] > - Updated camcc drivers for SM8450, SM8550, SM8650 and X1E80100 targets > with support to configure PLLs from common code and added MXC power > domain in corresponding camcc DT nodes. [Bryan] > - Added Dmitry and Bryan R-By tags received on videocc DT node changes in v1 > - Link to v2: https://lore.kernel.org/r/20250306-videocc-pll-multi-pd-voting-v2-0-0cd00612bc0e@quicinc.com > > Changes in v2: > - Added support to handle rpm, PLL configuration and enable critical > clocks from qcom_cc_really_probe() in common code as per v1 commments > from Bryan, Konrad and Dmitry > - Added patches to configure PLLs from common code > - Updated the SM8450, SM8550 videocc patches to use the newly > added support to handle rpm, configure PLLs from common code > - Split the DT change for each target separately as per > Dmitry comments > - Added R-By and A-By tags received on v1 > - Link to v1: https://lore.kernel.org/r/20250218-videocc-pll-multi-pd-voting-v1-0-cfe6289ea29b@quicinc.com > > --- > Jagadeesh Kona (15): > dt-bindings: clock: qcom,sm8450-videocc: Add MXC power domain > dt-bindings: clock: qcom,sm8450-camcc: Move sc8280xp camcc to sa8775p camcc > clk: qcom: common: Handle runtime power management in qcom_cc_really_probe > clk: qcom: common: Add support to configure clk regs in qcom_cc_really_probe > clk: qcom: videocc-sm8450: Move PLL & clk configuration to really probe > clk: qcom: videocc-sm8550: Move PLL & clk configuration to really probe > clk: qcom: camcc-sm8450: Move PLL & clk configuration to really probe > clk: qcom: camcc-sm8550: Move PLL & clk configuration to really probe > clk: qcom: camcc-sm8650: Move PLL & clk configuration to really probe > clk: qcom: camcc-x1e80100: Move PLL & clk configuration to really probe > arm64: dts: qcom: sm8450: Additionally manage MXC power domain in videocc > arm64: dts: qcom: sm8550: Additionally manage MXC power domain in videocc > arm64: dts: qcom: sm8650: Additionally manage MXC power domain in videocc > arm64: dts: qcom: sm8450: Additionally manage MXC power domain in camcc > arm64: dts: qcom: sm8650: Additionally manage MXC power domain in camcc > > Taniya Das (1): > clk: qcom: clk-alpha-pll: Add support for common PLL configuration function > > Vladimir Zapolskiy (2): > dt-bindings: clock: qcom,sm8450-camcc: Allow to specify two power domains > arm64: dts: qcom: sm8550: Additionally manage MXC power domain in camcc > > .../bindings/clock/qcom,sa8775p-camcc.yaml | 15 ++++ > .../bindings/clock/qcom,sm8450-camcc.yaml | 20 +++-- > .../bindings/clock/qcom,sm8450-videocc.yaml | 18 +++-- > arch/arm64/boot/dts/qcom/sm8450.dtsi | 12 ++- > arch/arm64/boot/dts/qcom/sm8550.dtsi | 12 ++- > arch/arm64/boot/dts/qcom/sm8650.dtsi | 6 +- > drivers/clk/qcom/camcc-sm8450.c | 89 +++++++++++----------- > drivers/clk/qcom/camcc-sm8550.c | 85 +++++++++++---------- > drivers/clk/qcom/camcc-sm8650.c | 83 ++++++++++---------- > drivers/clk/qcom/camcc-x1e80100.c | 67 ++++++++-------- > drivers/clk/qcom/clk-alpha-pll.c | 57 ++++++++++++++ > drivers/clk/qcom/clk-alpha-pll.h | 3 + > drivers/clk/qcom/common.c | 81 +++++++++++++++++--- > drivers/clk/qcom/common.h | 10 +++ > drivers/clk/qcom/videocc-sm8450.c | 58 ++++++-------- > drivers/clk/qcom/videocc-sm8550.c | 66 ++++++++-------- > 16 files changed, 421 insertions(+), 261 deletions(-) > --- > base-commit: 138cfc44b3c4a5fb800388c6e27be169970fb9f7 > change-id: 20250218-videocc-pll-multi-pd-voting-d614dce910e7 > > Best regards, > -- > Jagadeesh Kona <quic_jkona@quicinc.com> > > Can we merge this series now. Looks ready. --- bod
On Fri, 30 May 2025 18:50:45 +0530, Jagadeesh Kona wrote:
> In recent QCOM chipsets, PLLs require more than one power domain to be
> kept ON to configure the PLL. But the current code doesn't enable all
> the required power domains while configuring the PLLs, this leads to
> functional issues due to suboptimal settings of PLLs.
>
> To address this, add support for handling runtime power management,
> configuring plls and enabling critical clocks from qcom_cc_really_probe.
> The clock controller can specify PLLs, critical clocks, and runtime PM
> requirements using the descriptor data. The code in qcom_cc_really_probe()
> ensures all necessary power domains are enabled before configuring PLLs
> or critical clocks.
>
> [...]
Applied, thanks!
[01/18] dt-bindings: clock: qcom,sm8450-videocc: Add MXC power domain
commit: 1a42f4d4bb92ea961c58599bac837fb8b377a296
[02/18] dt-bindings: clock: qcom,sm8450-camcc: Allow to specify two power domains
commit: a02a8f8cb7f6f54b077a6f9eb74ccd840b472416
[03/18] dt-bindings: clock: qcom,sm8450-camcc: Move sc8280xp camcc to sa8775p camcc
commit: 842fa748291553d2f56410034991d0eb36b70900
[04/18] clk: qcom: clk-alpha-pll: Add support for common PLL configuration function
commit: 0f698c16358ef300ed28a608368b89a4f6a8623a
[05/18] clk: qcom: common: Handle runtime power management in qcom_cc_really_probe
commit: c0b6627369bcfec151ccbd091f9ff1cadb1d40c1
[06/18] clk: qcom: common: Add support to configure clk regs in qcom_cc_really_probe
commit: 452ae64997dd1db1fe9bec2e7bd65b33338e7a6b
[07/18] clk: qcom: videocc-sm8450: Move PLL & clk configuration to really probe
commit: 512af5bf312efe09698de0870e99c0cec4d13e21
[08/18] clk: qcom: videocc-sm8550: Move PLL & clk configuration to really probe
commit: a9dc2cc7279a1967f37192a2f954e7111bfa61b7
[09/18] clk: qcom: camcc-sm8450: Move PLL & clk configuration to really probe
commit: eb65d754eb5eaeab7db87ce7e64dab27b7d156d8
[10/18] clk: qcom: camcc-sm8550: Move PLL & clk configuration to really probe
commit: adb50c762f3a513a363d91722dbd8d1b4afc5f10
[11/18] clk: qcom: camcc-sm8650: Move PLL & clk configuration to really probe
commit: 3f8dd231e60b706fc9395edbf0186b7a0756f45d
[12/18] clk: qcom: camcc-x1e80100: Move PLL & clk configuration to really probe
commit: d7eddaf0ed07e79ffdfd20acb2f6f2ca53e7851b
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
On 6/12/2025 9:30 AM, Bjorn Andersson wrote: > > On Fri, 30 May 2025 18:50:45 +0530, Jagadeesh Kona wrote: >> In recent QCOM chipsets, PLLs require more than one power domain to be >> kept ON to configure the PLL. But the current code doesn't enable all >> the required power domains while configuring the PLLs, this leads to >> functional issues due to suboptimal settings of PLLs. >> >> To address this, add support for handling runtime power management, >> configuring plls and enabling critical clocks from qcom_cc_really_probe. >> The clock controller can specify PLLs, critical clocks, and runtime PM >> requirements using the descriptor data. The code in qcom_cc_really_probe() >> ensures all necessary power domains are enabled before configuring PLLs >> or critical clocks. >> >> [...] > > Applied, thanks! > > [01/18] dt-bindings: clock: qcom,sm8450-videocc: Add MXC power domain > commit: 1a42f4d4bb92ea961c58599bac837fb8b377a296 > [02/18] dt-bindings: clock: qcom,sm8450-camcc: Allow to specify two power domains > commit: a02a8f8cb7f6f54b077a6f9eb74ccd840b472416 > [03/18] dt-bindings: clock: qcom,sm8450-camcc: Move sc8280xp camcc to sa8775p camcc > commit: 842fa748291553d2f56410034991d0eb36b70900 > [04/18] clk: qcom: clk-alpha-pll: Add support for common PLL configuration function > commit: 0f698c16358ef300ed28a608368b89a4f6a8623a > [05/18] clk: qcom: common: Handle runtime power management in qcom_cc_really_probe > commit: c0b6627369bcfec151ccbd091f9ff1cadb1d40c1 > [06/18] clk: qcom: common: Add support to configure clk regs in qcom_cc_really_probe > commit: 452ae64997dd1db1fe9bec2e7bd65b33338e7a6b > [07/18] clk: qcom: videocc-sm8450: Move PLL & clk configuration to really probe > commit: 512af5bf312efe09698de0870e99c0cec4d13e21 > [08/18] clk: qcom: videocc-sm8550: Move PLL & clk configuration to really probe > commit: a9dc2cc7279a1967f37192a2f954e7111bfa61b7 > [09/18] clk: qcom: camcc-sm8450: Move PLL & clk configuration to really probe > commit: eb65d754eb5eaeab7db87ce7e64dab27b7d156d8 > [10/18] clk: qcom: camcc-sm8550: Move PLL & clk configuration to really probe > commit: adb50c762f3a513a363d91722dbd8d1b4afc5f10 > [11/18] clk: qcom: camcc-sm8650: Move PLL & clk configuration to really probe > commit: 3f8dd231e60b706fc9395edbf0186b7a0756f45d > [12/18] clk: qcom: camcc-x1e80100: Move PLL & clk configuration to really probe > commit: d7eddaf0ed07e79ffdfd20acb2f6f2ca53e7851b > > Best regards, Hi Bjorn, Thanks for picking these patches. However, the dt-bindings patches are closely linked with the DT patches in this series and needs to be picked together. The dt-bindings changes adds multiple power domains support for clock controllers, and without the corresponding DT patches, dtbs_check will give warnings. Can you please help to pick DT patches as well? Thanks, Jagadeesh
On 12/06/2025 12:03, Jagadeesh Kona wrote: > > > On 6/12/2025 9:30 AM, Bjorn Andersson wrote: >> >> On Fri, 30 May 2025 18:50:45 +0530, Jagadeesh Kona wrote: >>> In recent QCOM chipsets, PLLs require more than one power domain to be >>> kept ON to configure the PLL. But the current code doesn't enable all >>> the required power domains while configuring the PLLs, this leads to >>> functional issues due to suboptimal settings of PLLs. >>> >>> To address this, add support for handling runtime power management, >>> configuring plls and enabling critical clocks from qcom_cc_really_probe. >>> The clock controller can specify PLLs, critical clocks, and runtime PM >>> requirements using the descriptor data. The code in qcom_cc_really_probe() >>> ensures all necessary power domains are enabled before configuring PLLs >>> or critical clocks. >>> >>> [...] >> >> Applied, thanks! >> >> [01/18] dt-bindings: clock: qcom,sm8450-videocc: Add MXC power domain >> commit: 1a42f4d4bb92ea961c58599bac837fb8b377a296 >> [02/18] dt-bindings: clock: qcom,sm8450-camcc: Allow to specify two power domains >> commit: a02a8f8cb7f6f54b077a6f9eb74ccd840b472416 >> [03/18] dt-bindings: clock: qcom,sm8450-camcc: Move sc8280xp camcc to sa8775p camcc >> commit: 842fa748291553d2f56410034991d0eb36b70900 >> [04/18] clk: qcom: clk-alpha-pll: Add support for common PLL configuration function >> commit: 0f698c16358ef300ed28a608368b89a4f6a8623a >> [05/18] clk: qcom: common: Handle runtime power management in qcom_cc_really_probe >> commit: c0b6627369bcfec151ccbd091f9ff1cadb1d40c1 >> [06/18] clk: qcom: common: Add support to configure clk regs in qcom_cc_really_probe >> commit: 452ae64997dd1db1fe9bec2e7bd65b33338e7a6b >> [07/18] clk: qcom: videocc-sm8450: Move PLL & clk configuration to really probe >> commit: 512af5bf312efe09698de0870e99c0cec4d13e21 >> [08/18] clk: qcom: videocc-sm8550: Move PLL & clk configuration to really probe >> commit: a9dc2cc7279a1967f37192a2f954e7111bfa61b7 >> [09/18] clk: qcom: camcc-sm8450: Move PLL & clk configuration to really probe >> commit: eb65d754eb5eaeab7db87ce7e64dab27b7d156d8 >> [10/18] clk: qcom: camcc-sm8550: Move PLL & clk configuration to really probe >> commit: adb50c762f3a513a363d91722dbd8d1b4afc5f10 >> [11/18] clk: qcom: camcc-sm8650: Move PLL & clk configuration to really probe >> commit: 3f8dd231e60b706fc9395edbf0186b7a0756f45d >> [12/18] clk: qcom: camcc-x1e80100: Move PLL & clk configuration to really probe >> commit: d7eddaf0ed07e79ffdfd20acb2f6f2ca53e7851b >> >> Best regards, > > > Hi Bjorn, > > Thanks for picking these patches. However, the dt-bindings patches are closely linked with > the DT patches in this series and needs to be picked together. The dt-bindings changes adds DT bindings are the DT patches. What do you mean by DT? DTS? If so, then you introduce regressions without explaining this at all in cover letter or patches. > multiple power domains support for clock controllers, and without the corresponding DT > patches, dtbs_check will give warnings. > > Can you please help to pick DT patches as well? Please read soc maintainer profile explaining how DTS is being organized. Best regards, Krzysztof
On 6/12/2025 4:22 PM, Krzysztof Kozlowski wrote: > On 12/06/2025 12:03, Jagadeesh Kona wrote: >> >> >> On 6/12/2025 9:30 AM, Bjorn Andersson wrote: >>> >>> On Fri, 30 May 2025 18:50:45 +0530, Jagadeesh Kona wrote: >>>> In recent QCOM chipsets, PLLs require more than one power domain to be >>>> kept ON to configure the PLL. But the current code doesn't enable all >>>> the required power domains while configuring the PLLs, this leads to >>>> functional issues due to suboptimal settings of PLLs. >>>> >>>> To address this, add support for handling runtime power management, >>>> configuring plls and enabling critical clocks from qcom_cc_really_probe. >>>> The clock controller can specify PLLs, critical clocks, and runtime PM >>>> requirements using the descriptor data. The code in qcom_cc_really_probe() >>>> ensures all necessary power domains are enabled before configuring PLLs >>>> or critical clocks. >>>> >>>> [...] >>> >>> Applied, thanks! >>> >>> [01/18] dt-bindings: clock: qcom,sm8450-videocc: Add MXC power domain >>> commit: 1a42f4d4bb92ea961c58599bac837fb8b377a296 >>> [02/18] dt-bindings: clock: qcom,sm8450-camcc: Allow to specify two power domains >>> commit: a02a8f8cb7f6f54b077a6f9eb74ccd840b472416 >>> [03/18] dt-bindings: clock: qcom,sm8450-camcc: Move sc8280xp camcc to sa8775p camcc >>> commit: 842fa748291553d2f56410034991d0eb36b70900 >>> [04/18] clk: qcom: clk-alpha-pll: Add support for common PLL configuration function >>> commit: 0f698c16358ef300ed28a608368b89a4f6a8623a >>> [05/18] clk: qcom: common: Handle runtime power management in qcom_cc_really_probe >>> commit: c0b6627369bcfec151ccbd091f9ff1cadb1d40c1 >>> [06/18] clk: qcom: common: Add support to configure clk regs in qcom_cc_really_probe >>> commit: 452ae64997dd1db1fe9bec2e7bd65b33338e7a6b >>> [07/18] clk: qcom: videocc-sm8450: Move PLL & clk configuration to really probe >>> commit: 512af5bf312efe09698de0870e99c0cec4d13e21 >>> [08/18] clk: qcom: videocc-sm8550: Move PLL & clk configuration to really probe >>> commit: a9dc2cc7279a1967f37192a2f954e7111bfa61b7 >>> [09/18] clk: qcom: camcc-sm8450: Move PLL & clk configuration to really probe >>> commit: eb65d754eb5eaeab7db87ce7e64dab27b7d156d8 >>> [10/18] clk: qcom: camcc-sm8550: Move PLL & clk configuration to really probe >>> commit: adb50c762f3a513a363d91722dbd8d1b4afc5f10 >>> [11/18] clk: qcom: camcc-sm8650: Move PLL & clk configuration to really probe >>> commit: 3f8dd231e60b706fc9395edbf0186b7a0756f45d >>> [12/18] clk: qcom: camcc-x1e80100: Move PLL & clk configuration to really probe >>> commit: d7eddaf0ed07e79ffdfd20acb2f6f2ca53e7851b >>> >>> Best regards, >> >> >> Hi Bjorn, >> >> Thanks for picking these patches. However, the dt-bindings patches are closely linked with >> the DT patches in this series and needs to be picked together. The dt-bindings changes adds > > DT bindings are the DT patches. What do you mean by DT? DTS? If so, then > you introduce regressions without explaining this at all in cover letter > or patches. > >> multiple power domains support for clock controllers, and without the corresponding DT >> patches, dtbs_check will give warnings. >> >> Can you please help to pick DT patches as well? > > Please read soc maintainer profile explaining how DTS is being organized. > I apologize for not mentioning this details in cover letter. Here the dt-bindings documentation changes(patches 1-3) are only applied and the corresponding DTS changes(patches 13-18) are not yet applied via DTS tree, leading to dtbs_check warnings. Thanks, Jagadeesh > > Best regards, > Krzysztof
On Mon, Jun 16, 2025 at 12:55:47PM +0530, Jagadeesh Kona wrote: > > > On 6/12/2025 4:22 PM, Krzysztof Kozlowski wrote: > > On 12/06/2025 12:03, Jagadeesh Kona wrote: > >> > >> > >> On 6/12/2025 9:30 AM, Bjorn Andersson wrote: > >>> > >>> On Fri, 30 May 2025 18:50:45 +0530, Jagadeesh Kona wrote: > >>>> In recent QCOM chipsets, PLLs require more than one power domain to be > >>>> kept ON to configure the PLL. But the current code doesn't enable all > >>>> the required power domains while configuring the PLLs, this leads to > >>>> functional issues due to suboptimal settings of PLLs. > >>>> > >>>> To address this, add support for handling runtime power management, > >>>> configuring plls and enabling critical clocks from qcom_cc_really_probe. > >>>> The clock controller can specify PLLs, critical clocks, and runtime PM > >>>> requirements using the descriptor data. The code in qcom_cc_really_probe() > >>>> ensures all necessary power domains are enabled before configuring PLLs > >>>> or critical clocks. > >>>> > >>>> [...] > >>> > >>> Applied, thanks! > >>> > >>> [01/18] dt-bindings: clock: qcom,sm8450-videocc: Add MXC power domain > >>> commit: 1a42f4d4bb92ea961c58599bac837fb8b377a296 > >>> [02/18] dt-bindings: clock: qcom,sm8450-camcc: Allow to specify two power domains > >>> commit: a02a8f8cb7f6f54b077a6f9eb74ccd840b472416 > >>> [03/18] dt-bindings: clock: qcom,sm8450-camcc: Move sc8280xp camcc to sa8775p camcc > >>> commit: 842fa748291553d2f56410034991d0eb36b70900 > >>> [04/18] clk: qcom: clk-alpha-pll: Add support for common PLL configuration function > >>> commit: 0f698c16358ef300ed28a608368b89a4f6a8623a > >>> [05/18] clk: qcom: common: Handle runtime power management in qcom_cc_really_probe > >>> commit: c0b6627369bcfec151ccbd091f9ff1cadb1d40c1 > >>> [06/18] clk: qcom: common: Add support to configure clk regs in qcom_cc_really_probe > >>> commit: 452ae64997dd1db1fe9bec2e7bd65b33338e7a6b > >>> [07/18] clk: qcom: videocc-sm8450: Move PLL & clk configuration to really probe > >>> commit: 512af5bf312efe09698de0870e99c0cec4d13e21 > >>> [08/18] clk: qcom: videocc-sm8550: Move PLL & clk configuration to really probe > >>> commit: a9dc2cc7279a1967f37192a2f954e7111bfa61b7 > >>> [09/18] clk: qcom: camcc-sm8450: Move PLL & clk configuration to really probe > >>> commit: eb65d754eb5eaeab7db87ce7e64dab27b7d156d8 > >>> [10/18] clk: qcom: camcc-sm8550: Move PLL & clk configuration to really probe > >>> commit: adb50c762f3a513a363d91722dbd8d1b4afc5f10 > >>> [11/18] clk: qcom: camcc-sm8650: Move PLL & clk configuration to really probe > >>> commit: 3f8dd231e60b706fc9395edbf0186b7a0756f45d > >>> [12/18] clk: qcom: camcc-x1e80100: Move PLL & clk configuration to really probe > >>> commit: d7eddaf0ed07e79ffdfd20acb2f6f2ca53e7851b > >>> > >>> Best regards, > >> > >> > >> Hi Bjorn, > >> > >> Thanks for picking these patches. However, the dt-bindings patches are closely linked with > >> the DT patches in this series and needs to be picked together. The dt-bindings changes adds > > > > DT bindings are the DT patches. What do you mean by DT? DTS? If so, then > > you introduce regressions without explaining this at all in cover letter > > or patches. > > > >> multiple power domains support for clock controllers, and without the corresponding DT > >> patches, dtbs_check will give warnings. > >> > >> Can you please help to pick DT patches as well? > > > > Please read soc maintainer profile explaining how DTS is being organized. > > > > I apologize for not mentioning this details in cover letter. Here the dt-bindings documentation > changes(patches 1-3) are only applied and the corresponding DTS changes(patches 13-18) are not > yet applied via DTS tree, leading to dtbs_check warnings. > Mentioning this in the cover letter wouldn't change the fact that the binding is changing in an unexpected way. As the binding now express that 2 power-domains is required, the driver author would be free to expect that the loaded DTB has 2 power-domains specified. But the user might still have an older DTB on their system (exactly what dtbs_check is complaining about now). A quick look makes me think that it's because you removed the maxItems:1 which means that the properties needs to match completely. Changing this to minItems:1 should allow for both cases, I think. Can you please send a patch that fixes up the bindings to allow both the old and new case? Regards, Bjorn > Thanks, > Jagadeesh > > > > > Best regards, > > Krzysztof
On 6/17/2025 6:57 PM, Bjorn Andersson wrote: > On Mon, Jun 16, 2025 at 12:55:47PM +0530, Jagadeesh Kona wrote: >> >> >> On 6/12/2025 4:22 PM, Krzysztof Kozlowski wrote: >>> On 12/06/2025 12:03, Jagadeesh Kona wrote: >>>> >>>> >>>> On 6/12/2025 9:30 AM, Bjorn Andersson wrote: >>>>> >>>>> On Fri, 30 May 2025 18:50:45 +0530, Jagadeesh Kona wrote: >>>>>> In recent QCOM chipsets, PLLs require more than one power domain to be >>>>>> kept ON to configure the PLL. But the current code doesn't enable all >>>>>> the required power domains while configuring the PLLs, this leads to >>>>>> functional issues due to suboptimal settings of PLLs. >>>>>> >>>>>> To address this, add support for handling runtime power management, >>>>>> configuring plls and enabling critical clocks from qcom_cc_really_probe. >>>>>> The clock controller can specify PLLs, critical clocks, and runtime PM >>>>>> requirements using the descriptor data. The code in qcom_cc_really_probe() >>>>>> ensures all necessary power domains are enabled before configuring PLLs >>>>>> or critical clocks. >>>>>> >>>>>> [...] >>>>> >>>>> Applied, thanks! >>>>> >>>>> [01/18] dt-bindings: clock: qcom,sm8450-videocc: Add MXC power domain >>>>> commit: 1a42f4d4bb92ea961c58599bac837fb8b377a296 >>>>> [02/18] dt-bindings: clock: qcom,sm8450-camcc: Allow to specify two power domains >>>>> commit: a02a8f8cb7f6f54b077a6f9eb74ccd840b472416 >>>>> [03/18] dt-bindings: clock: qcom,sm8450-camcc: Move sc8280xp camcc to sa8775p camcc >>>>> commit: 842fa748291553d2f56410034991d0eb36b70900 >>>>> [04/18] clk: qcom: clk-alpha-pll: Add support for common PLL configuration function >>>>> commit: 0f698c16358ef300ed28a608368b89a4f6a8623a >>>>> [05/18] clk: qcom: common: Handle runtime power management in qcom_cc_really_probe >>>>> commit: c0b6627369bcfec151ccbd091f9ff1cadb1d40c1 >>>>> [06/18] clk: qcom: common: Add support to configure clk regs in qcom_cc_really_probe >>>>> commit: 452ae64997dd1db1fe9bec2e7bd65b33338e7a6b >>>>> [07/18] clk: qcom: videocc-sm8450: Move PLL & clk configuration to really probe >>>>> commit: 512af5bf312efe09698de0870e99c0cec4d13e21 >>>>> [08/18] clk: qcom: videocc-sm8550: Move PLL & clk configuration to really probe >>>>> commit: a9dc2cc7279a1967f37192a2f954e7111bfa61b7 >>>>> [09/18] clk: qcom: camcc-sm8450: Move PLL & clk configuration to really probe >>>>> commit: eb65d754eb5eaeab7db87ce7e64dab27b7d156d8 >>>>> [10/18] clk: qcom: camcc-sm8550: Move PLL & clk configuration to really probe >>>>> commit: adb50c762f3a513a363d91722dbd8d1b4afc5f10 >>>>> [11/18] clk: qcom: camcc-sm8650: Move PLL & clk configuration to really probe >>>>> commit: 3f8dd231e60b706fc9395edbf0186b7a0756f45d >>>>> [12/18] clk: qcom: camcc-x1e80100: Move PLL & clk configuration to really probe >>>>> commit: d7eddaf0ed07e79ffdfd20acb2f6f2ca53e7851b >>>>> >>>>> Best regards, >>>> >>>> >>>> Hi Bjorn, >>>> >>>> Thanks for picking these patches. However, the dt-bindings patches are closely linked with >>>> the DT patches in this series and needs to be picked together. The dt-bindings changes adds >>> >>> DT bindings are the DT patches. What do you mean by DT? DTS? If so, then >>> you introduce regressions without explaining this at all in cover letter >>> or patches. >>> >>>> multiple power domains support for clock controllers, and without the corresponding DT >>>> patches, dtbs_check will give warnings. >>>> >>>> Can you please help to pick DT patches as well? >>> >>> Please read soc maintainer profile explaining how DTS is being organized. >>> >> >> I apologize for not mentioning this details in cover letter. Here the dt-bindings documentation >> changes(patches 1-3) are only applied and the corresponding DTS changes(patches 13-18) are not >> yet applied via DTS tree, leading to dtbs_check warnings. >> > > Mentioning this in the cover letter wouldn't change the fact that the > binding is changing in an unexpected way. > > As the binding now express that 2 power-domains is required, the driver > author would be free to expect that the loaded DTB has 2 power-domains > specified. But the user might still have an older DTB on their system > (exactly what dtbs_check is complaining about now). > > A quick look makes me think that it's because you removed the maxItems:1 > which means that the properties needs to match completely. Changing this > to minItems:1 should allow for both cases, I think. > > > Can you please send a patch that fixes up the bindings to allow both the > old and new case? > Thanks Bjorn and Krzysztof for the info and suggestion. I tried adding minItems as 1 to power-domains and required-opps properties and dtbs_check is working fine now for both single and multi power-domains cases. I have posted the below series with this fixes: https://lore.kernel.org/all/20250618-sm8450-videocc-camcc-bindings-single-pd-fix-v1-0-02e83aeba280@quicinc.com/ Thanks, Jagadeesh > Regards, > Bjorn > >> Thanks, >> Jagadeesh >> >>> >>> Best regards, >>> Krzysztof
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