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Fri, 30 May 2025 13:21:07 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 54UDL6KI014607 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 30 May 2025 13:21:06 GMT Received: from [10.213.98.28] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 30 May 2025 06:21:01 -0700 From: Jagadeesh Kona Date: Fri, 30 May 2025 18:50:46 +0530 Subject: [PATCH v5 01/18] dt-bindings: clock: qcom,sm8450-videocc: Add MXC power domain Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250530-videocc-pll-multi-pd-voting-v5-1-02303b3a582d@quicinc.com> References: <20250530-videocc-pll-multi-pd-voting-v5-0-02303b3a582d@quicinc.com> In-Reply-To: <20250530-videocc-pll-multi-pd-voting-v5-0-02303b3a582d@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , "Vladimir Zapolskiy" , Dmitry Baryshkov CC: Ajit Pandey , Imran Shaik , Taniya Das , "Satya Priya Kakitapalli" , , , , , Krzysztof Kozlowski , Jagadeesh Kona , Bryan O'Donoghue X-Mailer: b4 0.14.2 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTMwMDExNiBTYWx0ZWRfX9Hh3CxFRBF4N MxFMobB0yLCa+ONAjlSu51bWwDgt8vsFKvf+QoCsf4PuSUtfqEXt/MlMEz8n6gDVoNXM2XMAZa0 RfRSrFKdag+/cF4QJeXIl3xpI50Ne6aMUSWnG6dsmy8yBiQBMCAD53TKjqKABin3dcLfhDO5DJi I5eXh6B2KVaWKpd+d2CIdDjBDSB8KpREly706LWh2lXvq3Kon2rg7Go0IwnYbcGQW7Os0qW4+JG gpPTcTFspDakNynQg3XEK6tnZIxKJGalprqJwxBCI4nBChR/NQHiCqOd0KKyWSq06JG7Lwb1Bw0 asEbtfEiiojnqjDCdGWRwk6On0XIMF1uQnbO19oWoVTdyIQms9WBO9XVspCtg6QoSLoryXi5tK1 JpJ0p1bu8xDkvEvxLJYqK/2Ejj8ZCcDIi9eZyiE6CBpZZ890wXwD7qNmqvIr82CS+LcN8rg+ X-Authority-Analysis: v=2.4 cv=Ybe95xRf c=1 sm=1 tr=0 ts=6839b0c3 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=KKAkSRfTAAAA:8 a=VwQbUJbxAAAA:8 a=Nwh09rWfvR_xP5f7LFwA:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: r1taEYSH1eLgFOyQteWZWPUY7I-H52Ka X-Proofpoint-ORIG-GUID: r1taEYSH1eLgFOyQteWZWPUY7I-H52Ka X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-30_05,2025-05-30_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 spamscore=0 priorityscore=1501 mlxlogscore=999 malwarescore=0 lowpriorityscore=0 clxscore=1015 phishscore=0 impostorscore=0 mlxscore=0 adultscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505300116 To configure the video PLLs and enable the video GDSCs on SM8450, SM8475, SM8550 and SM8650 platforms, the MXC rail must be ON along with MMCX. Therefore, update the videocc bindings to include the MXC power domain on these platforms. Fixes: 1e910b2ba0ed ("dt-bindings: clock: qcom: Add SM8450 video clock cont= roller") Signed-off-by: Jagadeesh Kona Reviewed-by: Bryan O'Donoghue Acked-by: Rob Herring (Arm) --- .../devicetree/bindings/clock/qcom,sm8450-videocc.yaml | 18 ++++++++++++--= ---- 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.ya= ml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml index 62714fa54db82491a7a108f7f18a253d737f8d61..0d99178332cb99d3f02f50605e1= 9b9b26e3ec807 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml @@ -32,14 +32,18 @@ properties: - description: Video AHB clock from GCC =20 power-domains: - maxItems: 1 description: - MMCX power domain. + Power domains required for the clock controller to operate + items: + - description: MMCX power domain + - description: MXC power domain =20 required-opps: - maxItems: 1 description: - A phandle to an OPP node describing required MMCX performance point. + OPP nodes that describe required performance points on power domains + items: + - description: MMCX performance point + - description: MXC performance point =20 required: - compatible @@ -72,8 +76,10 @@ examples: reg =3D <0x0aaf0000 0x10000>; clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_VIDEO_AHB_CLK>; - power-domains =3D <&rpmhpd RPMHPD_MMCX>; - required-opps =3D <&rpmhpd_opp_low_svs>; + power-domains =3D <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps =3D <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; #clock-cells =3D <1>; #reset-cells =3D <1>; #power-domain-cells =3D <1>; --=20 2.34.1 From nobody Tue Dec 16 22:33:08 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5527F70830; Fri, 30 May 2025 13:21:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748611278; cv=none; b=VTFlF9XZBV4GvarcAjci2+RWu2DwOyjpDsRIGANfdrgORpaTva6PSfIQCQ1OO40NyQDGWZIDzjfp8uubNkNmC8NlIGWhOHCFmg8AOKjUqzTi0+nCaPdpGUwsv2G1iwtJT+ofW+NngwhVlUuy9/QRG1x+JTu1kkaJf9y7bftArbM= ARC-Message-Signature: i=1; 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Fri, 30 May 2025 13:21:12 GMT Received: from [10.213.98.28] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 30 May 2025 06:21:06 -0700 From: Jagadeesh Kona Date: Fri, 30 May 2025 18:50:47 +0530 Subject: [PATCH v5 02/18] dt-bindings: clock: qcom,sm8450-camcc: Allow to specify two power domains Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250530-videocc-pll-multi-pd-voting-v5-2-02303b3a582d@quicinc.com> References: <20250530-videocc-pll-multi-pd-voting-v5-0-02303b3a582d@quicinc.com> In-Reply-To: <20250530-videocc-pll-multi-pd-voting-v5-0-02303b3a582d@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , "Vladimir Zapolskiy" , Dmitry Baryshkov CC: Ajit Pandey , Imran Shaik , Taniya Das , "Satya Priya Kakitapalli" , , , , , Krzysztof Kozlowski , Jagadeesh Kona , Bryan O'Donoghue X-Mailer: b4 0.14.2 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=OslPyz/t c=1 sm=1 tr=0 ts=6839b0c9 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=KKAkSRfTAAAA:8 a=COk6AnOGAAAA:8 a=VNckzqIK-Xfz9zBCpKcA:9 a=QEXdDO2ut3YA:10 a=cvBusfyB2V15izCimMoJ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: x9zy4aIHhdhTajYnVSszW4R7bYCFBXGM X-Proofpoint-GUID: x9zy4aIHhdhTajYnVSszW4R7bYCFBXGM X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTMwMDExNiBTYWx0ZWRfX/SRSLqeTM55S kjtFi4BsbPs4Di/ViLL+zExEmBJLbpvBABP9mWrS5ro1d0uf8ZCQcvJJvrbIR/SYq9Y9aPYLMy4 huPtJ3U8sn0K8+j0YiZE/MM1jHxEYrBTg2setTSX833Jwq0XvyaT2+GGxa5DSOVgjzTjSbzl9DW UaT6q32oOoDvPNLx8belwiECBh/O6alGXwBdcQ0cIYs2xLjxVYyCp0FPzwVR14PPxNrUJaB4zsb q++FN8HsEr9RurPqx71T1TmR+Ysz9K4+jVvBUs6HcmnogCDXFYGZcoCFtx//SKvs7Djo6BIXOch P6tDk6Rw5covG/+vofiVkQIkB2IFwycGYVVWK3pnYYxjgM8Eam8cQAQFpxddfXMWMUwVf8LgVRr 2jfprIlXeMw521hqiumIEvwxzzTgUgqGxqQPJgSb2mgvvMqcP4mT4Hc8w5EcY0pJALYclB55 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-30_05,2025-05-30_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 mlxlogscore=985 adultscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 clxscore=1015 mlxscore=0 lowpriorityscore=0 spamscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505300116 From: Vladimir Zapolskiy To configure the camera PLLs and enable the camera GDSCs on SM8450, SM8475, SM8550 and SM8650 platforms, the MXC rail must be ON along with MMCX. Therefore, update the camcc bindings to include the MXC power domain on these platforms. Fixes: 9cbc64745fc6 ("dt-bindings: clock: qcom: Add SM8550 camera clock con= troller") Signed-off-by: Vladimir Zapolskiy Reviewed-by: Krzysztof Kozlowski Reviewed-by: Bryan O'Donoghue Signed-off-by: Jagadeesh Kona --- .../devicetree/bindings/clock/qcom,sm8450-camcc.yaml | 18 ++++++++++++--= ---- 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml= b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml index 9e79f8fec437b9aecb5103092f6ff2ad1cd42626..3fded6aa712fc1920c4c4a92354= 5901ba804c42f 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml @@ -37,14 +37,18 @@ properties: - description: Sleep clock source =20 power-domains: - maxItems: 1 description: - A phandle and PM domain specifier for the MMCX power domain. + Power domains required for the clock controller to operate + items: + - description: MMCX power domain + - description: MXC power domain =20 required-opps: - maxItems: 1 description: - A phandle to an OPP node describing required MMCX performance point. + OPP nodes that describe required performance points on power domains + items: + - description: MMCX performance point + - description: MXC performance point =20 reg: maxItems: 1 @@ -82,8 +86,10 @@ examples: <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; 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Hence move SC8280XP camcc from SM8450 to SA8775P camcc, to have single power domain support. SA8775P camcc doesn't support required-opps property currently but SC8280XP camcc need that property, so add required-opps based on SC8280XP camcc conditional check in SA8775P camcc bindings. Reviewed-by: Bryan O'Donoghue Reviewed-by: Dmitry Baryshkov Signed-off-by: Jagadeesh Kona Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/clock/qcom,sa8775p-camcc.yaml | 15 +++++++++++= ++++ .../devicetree/bindings/clock/qcom,sm8450-camcc.yaml | 2 -- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,sa8775p-camcc.yam= l b/Documentation/devicetree/bindings/clock/qcom,sa8775p-camcc.yaml index 81623f59d11d73839e5c551411a52427e2f28415..f42ccb6627a387ee0d0238ebd1f= cd1cdf64c5676 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sa8775p-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sa8775p-camcc.yaml @@ -17,12 +17,14 @@ description: | See also: include/dt-bindings/clock/qcom,qcs8300-camcc.h include/dt-bindings/clock/qcom,sa8775p-camcc.h + include/dt-bindings/clock/qcom,sc8280xp-camcc.h =20 properties: compatible: enum: - qcom,qcs8300-camcc - qcom,sa8775p-camcc + - qcom,sc8280xp-camcc =20 clocks: items: @@ -35,6 +37,11 @@ properties: maxItems: 1 description: MMCX power domain =20 + required-opps: + description: + OPP node describing required MMCX performance point. + maxItems: 1 + required: - compatible - clocks @@ -43,6 +50,14 @@ required: =20 allOf: - $ref: qcom,gcc.yaml# + - if: + properties: + compatible: + contains: + const: qcom,sc8280xp-camcc + then: + required: + - required-opps =20 unevaluatedProperties: false =20 diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml= b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml index 3fded6aa712fc1920c4c4a923545901ba804c42f..c1e06f39431e68a3cd2f6c2dba8= 4be2a3c143bb1 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml @@ -15,7 +15,6 @@ description: | domains on SM8450. =20 See also: - include/dt-bindings/clock/qcom,sc8280xp-camcc.h include/dt-bindings/clock/qcom,sm8450-camcc.h include/dt-bindings/clock/qcom,sm8550-camcc.h include/dt-bindings/clock/qcom,sm8650-camcc.h @@ -23,7 +22,6 @@ description: | properties: compatible: enum: - - qcom,sc8280xp-camcc - qcom,sm8450-camcc - qcom,sm8475-camcc - qcom,sm8550-camcc --=20 2.34.1 From nobody Tue Dec 16 22:33:08 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5219970830; 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Fri, 30 May 2025 13:21:25 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 54UDLOjU012017 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 30 May 2025 13:21:24 GMT Received: from [10.213.98.28] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 30 May 2025 06:21:18 -0700 From: Jagadeesh Kona Date: Fri, 30 May 2025 18:50:49 +0530 Subject: [PATCH v5 04/18] clk: qcom: clk-alpha-pll: Add support for common PLL configuration function Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250530-videocc-pll-multi-pd-voting-v5-4-02303b3a582d@quicinc.com> References: <20250530-videocc-pll-multi-pd-voting-v5-0-02303b3a582d@quicinc.com> In-Reply-To: <20250530-videocc-pll-multi-pd-voting-v5-0-02303b3a582d@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , "Vladimir Zapolskiy" , Dmitry Baryshkov CC: Ajit Pandey , Imran Shaik , Taniya Das , "Satya Priya Kakitapalli" , , , , , Krzysztof Kozlowski , Jagadeesh Kona , Bryan O'Donoghue , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: f4fdO6qdbkn_ru8hNj7O0EfvzkyzOx6v X-Proofpoint-ORIG-GUID: f4fdO6qdbkn_ru8hNj7O0EfvzkyzOx6v X-Authority-Analysis: v=2.4 cv=X8pSKHTe c=1 sm=1 tr=0 ts=6839b0d5 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=JQl2qjEAfWPE5jP6FgYA:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTMwMDExNiBTYWx0ZWRfXyh6AX1siuamb kW+1qUsO3xGuSHAkgCClIM/X1GAgTqVubiODBrA1frh0YVMw1G8cXxn4EPrtRxSMe4EfGEycvfc UAUGdA03W0pm9a+EGJ+92q3yc1fUX4b3OE3+T+CkdkaxDQA8XZoMc+I+8Ym2tbcKP9VDCc5Ddjq zuC0463r3K+JRF64lOQRjOraXlUz5UzwyGcg+s5jLN9cop8f8KiPOeH0OFjfHLD+iv3jdyB4ENl IY7wFxa5MPx/TlHDdKOOsGjG8v+eMmifXwXYceqFDWpB+G1DuLZ2m1aB7VN/njAfCGrW+gzYC2+ t2WFGois9TgIArrZoQTTJDp4pT5WALd4H7FMlzkk1OCghSGCWNysuU2xR1u9NL3HHBFOl0hwnhz 0970jAmAAcM9f9bCDLUi+3VdsN4WnA7X+llzC7rHI+Xv9am1jsH3hYtFh/26oLPh2fYZ+rdN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-30_05,2025-05-30_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 lowpriorityscore=0 phishscore=0 spamscore=0 adultscore=0 impostorscore=0 bulkscore=0 mlxlogscore=999 suspectscore=0 clxscore=1015 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505300116 From: Taniya Das To properly configure the PLLs on recent chipsets, it often requires more than one power domain to be kept ON. The support to enable multiple power domains is being added in qcom_cc_really_probe() and PLLs should be configured post all the required power domains are enabled. Hence integrate PLL configuration into clk_alpha_pll structure and add support for qcom_clk_alpha_pll_configure() function which can be called from qcom_cc_really_probe() to configure the clock controller PLLs after all required power domains are enabled. Signed-off-by: Taniya Das Reviewed-by: Dmitry Baryshkov Signed-off-by: Jagadeesh Kona --- drivers/clk/qcom/clk-alpha-pll.c | 57 ++++++++++++++++++++++++++++++++++++= ++++ drivers/clk/qcom/clk-alpha-pll.h | 3 +++ 2 files changed, 60 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-= pll.c index cec0afea8e446010f0d4140d4ef63121706dde47..d8e1cd1263317814da2d0414600= 988de4b87c56f 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -63,6 +63,8 @@ #define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE]) #define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC]) =20 +#define GET_PLL_TYPE(pll) (((pll)->regs - clk_alpha_pll_regs[0]) / PLL_OFF= _MAX_REGS) + const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] =3D { [CLK_ALPHA_PLL_TYPE_DEFAULT] =3D { [PLL_OFF_L_VAL] =3D 0x04, @@ -2960,3 +2962,58 @@ const struct clk_ops clk_alpha_pll_regera_ops =3D { .set_rate =3D clk_zonda_pll_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_regera_ops); + +void qcom_clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap= *regmap) +{ + const struct clk_init_data *init =3D pll->clkr.hw.init; + + switch (GET_PLL_TYPE(pll)) { + case CLK_ALPHA_PLL_TYPE_LUCID_OLE: + clk_lucid_ole_pll_configure(pll, regmap, pll->config); + break; + case CLK_ALPHA_PLL_TYPE_LUCID_EVO: + clk_lucid_evo_pll_configure(pll, regmap, pll->config); + break; + case CLK_ALPHA_PLL_TYPE_TAYCAN_ELU: + clk_taycan_elu_pll_configure(pll, regmap, pll->config); + break; + case CLK_ALPHA_PLL_TYPE_RIVIAN_EVO: + clk_rivian_evo_pll_configure(pll, regmap, pll->config); + break; + case CLK_ALPHA_PLL_TYPE_TRION: + clk_trion_pll_configure(pll, regmap, pll->config); + break; + case CLK_ALPHA_PLL_TYPE_HUAYRA_2290: + clk_huayra_2290_pll_configure(pll, regmap, pll->config); + break; + case CLK_ALPHA_PLL_TYPE_FABIA: + clk_fabia_pll_configure(pll, regmap, pll->config); + break; + case CLK_ALPHA_PLL_TYPE_AGERA: + clk_agera_pll_configure(pll, regmap, pll->config); + break; + case CLK_ALPHA_PLL_TYPE_PONGO_ELU: + clk_pongo_elu_pll_configure(pll, regmap, pll->config); + break; + case CLK_ALPHA_PLL_TYPE_ZONDA: + case CLK_ALPHA_PLL_TYPE_ZONDA_OLE: + clk_zonda_pll_configure(pll, regmap, pll->config); + break; + case CLK_ALPHA_PLL_TYPE_STROMER: + case CLK_ALPHA_PLL_TYPE_STROMER_PLUS: + clk_stromer_pll_configure(pll, regmap, pll->config); + break; + case CLK_ALPHA_PLL_TYPE_DEFAULT: + case CLK_ALPHA_PLL_TYPE_DEFAULT_EVO: + case CLK_ALPHA_PLL_TYPE_HUAYRA: + case CLK_ALPHA_PLL_TYPE_HUAYRA_APSS: + case CLK_ALPHA_PLL_TYPE_BRAMMO: + case CLK_ALPHA_PLL_TYPE_BRAMMO_EVO: + clk_alpha_pll_configure(pll, regmap, pll->config); + break; + default: + WARN(1, "%s: invalid pll type\n", init->name); + break; + } +} +EXPORT_SYMBOL_GPL(qcom_clk_alpha_pll_configure); diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-= pll.h index 79aca8525262211ae5295245427d4540abf1e09a..7f35aaa7a35d88411beb11fd2be= 5d5dd5bfbe066 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -81,6 +81,7 @@ struct pll_vco { * struct clk_alpha_pll - phase locked loop (PLL) * @offset: base address of registers * @regs: alpha pll register map (see @clk_alpha_pll_regs) + * @config: array of pll settings * @vco_table: array of VCO settings * @num_vco: number of VCO settings in @vco_table * @flags: bitmask to indicate features supported by the hardware @@ -90,6 +91,7 @@ struct clk_alpha_pll { u32 offset; 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Fri, 30 May 2025 13:21:31 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 54UDLUT3031371 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 30 May 2025 13:21:30 GMT Received: from [10.213.98.28] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 30 May 2025 06:21:24 -0700 From: Jagadeesh Kona Date: Fri, 30 May 2025 18:50:50 +0530 Subject: [PATCH v5 05/18] clk: qcom: common: Handle runtime power management in qcom_cc_really_probe Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250530-videocc-pll-multi-pd-voting-v5-5-02303b3a582d@quicinc.com> References: <20250530-videocc-pll-multi-pd-voting-v5-0-02303b3a582d@quicinc.com> In-Reply-To: <20250530-videocc-pll-multi-pd-voting-v5-0-02303b3a582d@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , "Vladimir Zapolskiy" , Dmitry Baryshkov CC: Ajit Pandey , Imran Shaik , Taniya Das , "Satya Priya Kakitapalli" , , , , , Krzysztof Kozlowski , Jagadeesh Kona , Bryan O'Donoghue , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: yD7yOlpCN-L8jg-mwplQONHc6Yt3ZCXz X-Proofpoint-ORIG-GUID: yD7yOlpCN-L8jg-mwplQONHc6Yt3ZCXz X-Authority-Analysis: v=2.4 cv=X8FSKHTe c=1 sm=1 tr=0 ts=6839b0db cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=COk6AnOGAAAA:8 a=EY_aa_sejuBYboou7r8A:9 a=QEXdDO2ut3YA:10 a=cvBusfyB2V15izCimMoJ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTMwMDExNiBTYWx0ZWRfX8kLPQN+M6i6F 5uFA/CH6/GhghyC/vz4PGlwsZMZaWEka13O3cx+cyXTeLUJ0eG39q1CoasWuCXfxjExAP8dZyux Rpgx9n1hJJIwU96NCWzYDrggyQkof8ovNUFh9xpnUhiOcjVF4gEU92BJy61sNajz7epL3G9MX8m v6tZVPMXhoY/zXpxA0asLEoK+D6H1ZA0YQUAYIESlkpazOAjdy6drOr5Ai/yRrr6hVqgxcWl6A4 6GLUc0mkMWZEagAslBJw9DfGsYk8Rq5OQfzETSHV1wyfHnWs+1Li7Z7nc883RKYr1HtVCOdLeuI z661BcKLeKY1DCEa1hqye3G0kKMwRFfqgp7ivHy44a5y6+dzGESYxymB8M93jskdPi/gViu73Vx qN9kTbb0MD07aCY4L+oFnwaAdfvVjo7oTstpPCh/HYq4JLH54lpbvWQe5dRKz0u/vwDidlzx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-30_05,2025-05-30_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 phishscore=0 bulkscore=0 mlxlogscore=999 mlxscore=0 clxscore=1015 priorityscore=1501 spamscore=0 adultscore=0 malwarescore=0 lowpriorityscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505300116 Add support for runtime power management in qcom_cc_really_probe() to commonize it across all the clock controllers. The runtime power management is not required for all clock controllers, hence handle the rpm based on use_rpm flag in clock controller descriptor. Reviewed-by: Dmitry Baryshkov Reviewed-by: Bryan O'Donoghue Signed-off-by: Jagadeesh Kona --- drivers/clk/qcom/common.c | 37 ++++++++++++++++++++++++++++--------- drivers/clk/qcom/common.h | 1 + 2 files changed, 29 insertions(+), 9 deletions(-) diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c index 9e3380fd718198c9fe63d7361615a91c3ecb3d60..9cbf1c5296dad3ee5477a2f5a44= 5488707663b9d 100644 --- a/drivers/clk/qcom/common.c +++ b/drivers/clk/qcom/common.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include =20 @@ -304,6 +305,16 @@ int qcom_cc_really_probe(struct device *dev, if (ret < 0 && ret !=3D -EEXIST) return ret; =20 + if (desc->use_rpm) { + ret =3D devm_pm_runtime_enable(dev); + if (ret) + return ret; + + ret =3D pm_runtime_resume_and_get(dev); + if (ret) + return ret; + } + reset =3D &cc->reset; reset->rcdev.of_node =3D dev->of_node; reset->rcdev.ops =3D &qcom_reset_ops; @@ -314,23 +325,25 @@ int qcom_cc_really_probe(struct device *dev, =20 ret =3D devm_reset_controller_register(dev, &reset->rcdev); if (ret) - return ret; + goto put_rpm; =20 if (desc->gdscs && desc->num_gdscs) { scd =3D devm_kzalloc(dev, sizeof(*scd), GFP_KERNEL); - if (!scd) - return -ENOMEM; + if (!scd) { + ret =3D -ENOMEM; + goto put_rpm; + } scd->dev =3D dev; scd->scs =3D desc->gdscs; scd->num =3D desc->num_gdscs; scd->pd_list =3D cc->pd_list; ret =3D gdsc_register(scd, &reset->rcdev, regmap); if (ret) - return ret; + goto put_rpm; ret =3D devm_add_action_or_reset(dev, qcom_cc_gdsc_unregister, scd); if (ret) - return ret; + goto put_rpm; } =20 cc->rclks =3D rclks; @@ -341,7 +354,7 @@ int qcom_cc_really_probe(struct device *dev, for (i =3D 0; i < num_clk_hws; i++) { ret =3D devm_clk_hw_register(dev, clk_hws[i]); if (ret) - return ret; + goto put_rpm; } =20 for (i =3D 0; i < num_clks; i++) { @@ -350,14 +363,20 @@ int qcom_cc_really_probe(struct device *dev, =20 ret =3D devm_clk_register_regmap(dev, rclks[i]); if (ret) - return ret; + goto put_rpm; } =20 ret =3D devm_of_clk_add_hw_provider(dev, qcom_cc_clk_hw_get, cc); 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Fri, 30 May 2025 13:21:37 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 54UDLaTV028006 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 30 May 2025 13:21:36 GMT Received: from [10.213.98.28] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 30 May 2025 06:21:30 -0700 From: Jagadeesh Kona Date: Fri, 30 May 2025 18:50:51 +0530 Subject: [PATCH v5 06/18] clk: qcom: common: Add support to configure clk regs in qcom_cc_really_probe Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250530-videocc-pll-multi-pd-voting-v5-6-02303b3a582d@quicinc.com> References: <20250530-videocc-pll-multi-pd-voting-v5-0-02303b3a582d@quicinc.com> In-Reply-To: <20250530-videocc-pll-multi-pd-voting-v5-0-02303b3a582d@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , "Vladimir Zapolskiy" , Dmitry Baryshkov CC: Ajit Pandey , Imran Shaik , Taniya Das , "Satya Priya Kakitapalli" , , , , , Krzysztof Kozlowski , Jagadeesh Kona , Bryan O'Donoghue , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: PrXf_ZJISfLsLtkYTt8F8SlGUbPXZ9sg X-Proofpoint-ORIG-GUID: PrXf_ZJISfLsLtkYTt8F8SlGUbPXZ9sg X-Authority-Analysis: v=2.4 cv=X8FSKHTe c=1 sm=1 tr=0 ts=6839b0e1 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=VTlJxEOIkQDSKMlf4IcA:9 a=QEXdDO2ut3YA:10 a=cvBusfyB2V15izCimMoJ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTMwMDExNiBTYWx0ZWRfX5eg9/X4qdKsp xuVY/5xZjtbK9g8WbRyfqCTszB8CUbkU5iq/j5UdWs7LI7Zw0x4hud2YLo0brl9t8vAr2A8LtY2 xERaLONHd4+q/RgWFurIt55vusXgQRLjkXld/umc/54clV9FOwuRIsrSK9d24iBEsavyI1tRYO3 Ru7LIl+HZbMwC//CmRXD1/51nYaIR+V6yITUCDzlq6t/I9nfObleM60T15icxlxunCIpBYXs4XA 6iQyy4mNIBe8jz8CTNbA5nFOjHU7n1NivvXw7JA3hPToEwyqC0Yyv6gPo8jVM3adC06IiWVCWXb Rqu7iZO8pH9V0UBZOoCaozVgmcSjnAN6DviWSqrkMbHOxMOyHXQQXHnivM/QPIbiztqG4avhnYI iFi6yg3uoDAzSOhPeFxvHGkEz66yeb6cFbE67Lsx3yCCXF1pg8uZ41Haa1wQ0G+07/xnZQ6I X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-30_05,2025-05-30_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 phishscore=0 bulkscore=0 mlxlogscore=999 mlxscore=0 clxscore=1015 priorityscore=1501 spamscore=0 adultscore=0 malwarescore=0 lowpriorityscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505300116 Add support to configure PLLS and clk registers in qcom_cc_really_probe(). This ensures all required power domains are enabled and kept ON by runtime PM code in qcom_cc_really_probe() before configuring the PLLS or clock registers. Add support for qcom_cc_driver_data struct to maintain the clock controllers PLLs and CBCRs data, and a pointer of it can be stored in clock descriptor structure. If any clock controller driver requires to program some additional misc register settings, it can register the clk_regs_configure() callback in the driver data. Reviewed-by: Bryan O'Donoghue Reviewed-by: Dmitry Baryshkov Signed-off-by: Jagadeesh Kona Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/common.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ drivers/clk/qcom/common.h | 9 +++++++++ 2 files changed, 53 insertions(+) diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c index 9cbf1c5296dad3ee5477a2f5a445488707663b9d..b3838d885db25f183979576e5c6= 85c07dc6a7049 100644 --- a/drivers/clk/qcom/common.c +++ b/drivers/clk/qcom/common.c @@ -14,6 +14,8 @@ #include =20 #include "common.h" +#include "clk-alpha-pll.h" +#include "clk-branch.h" #include "clk-rcg.h" #include "clk-regmap.h" #include "reset.h" @@ -285,6 +287,40 @@ static int qcom_cc_icc_register(struct device *dev, desc->num_icc_hws, icd); } =20 +static int qcom_cc_clk_pll_configure(const struct qcom_cc_driver_data *dat= a, + struct regmap *regmap) +{ + const struct clk_init_data *init; + struct clk_alpha_pll *pll; + int i; + + for (i =3D 0; i < data->num_alpha_plls; i++) { + pll =3D data->alpha_plls[i]; + init =3D pll->clkr.hw.init; + + if (!pll->config || !pll->regs) { + pr_err("%s: missing pll config or regs\n", init->name); + return -EINVAL; + } + + qcom_clk_alpha_pll_configure(pll, regmap); + } + + return 0; +} + +static void qcom_cc_clk_regs_configure(struct device *dev, const struct qc= om_cc_driver_data *data, + struct regmap *regmap) +{ + int i; + + for (i =3D 0; i < data->num_clk_cbcrs; i++) + qcom_branch_set_clk_en(regmap, data->clk_cbcrs[i]); + + if (data->clk_regs_configure) + data->clk_regs_configure(dev, regmap); +} + int qcom_cc_really_probe(struct device *dev, const struct qcom_cc_desc *desc, struct regmap *regmap) { @@ -315,6 +351,14 @@ int qcom_cc_really_probe(struct device *dev, return ret; } =20 + if (desc->driver_data) { + ret =3D qcom_cc_clk_pll_configure(desc->driver_data, regmap); + if (ret) + goto put_rpm; + + qcom_cc_clk_regs_configure(dev, desc->driver_data, regmap); + } + reset =3D &cc->reset; reset->rcdev.of_node =3D dev->of_node; reset->rcdev.ops =3D &qcom_reset_ops; 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Fri, 30 May 2025 13:21:43 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 54UDLgNJ031517 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 30 May 2025 13:21:42 GMT Received: from [10.213.98.28] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 30 May 2025 06:21:36 -0700 From: Jagadeesh Kona Date: Fri, 30 May 2025 18:50:52 +0530 Subject: [PATCH v5 07/18] clk: qcom: videocc-sm8450: Move PLL & clk configuration to really probe Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250530-videocc-pll-multi-pd-voting-v5-7-02303b3a582d@quicinc.com> References: <20250530-videocc-pll-multi-pd-voting-v5-0-02303b3a582d@quicinc.com> In-Reply-To: <20250530-videocc-pll-multi-pd-voting-v5-0-02303b3a582d@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , "Vladimir Zapolskiy" , Dmitry Baryshkov CC: Ajit Pandey , Imran Shaik , Taniya Das , "Satya Priya Kakitapalli" , , , , , Krzysztof Kozlowski , Jagadeesh Kona , Bryan O'Donoghue , Dmitry Baryshkov , Konrad Dybcio X-Mailer: b4 0.14.2 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=GIgIEvNK c=1 sm=1 tr=0 ts=6839b0e7 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=NSTayzwvANHeSgS_AzkA:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: 2DKNznYdobWalRaP7BtO1k5458HRrwLw X-Proofpoint-GUID: 2DKNznYdobWalRaP7BtO1k5458HRrwLw X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTMwMDExNiBTYWx0ZWRfXzACy2aBDJJFU lG/kH0pZNaAEMCNPZiXWuheXOP7CXI6us5YZvVmtLdtPZyLtriimN9k4NGd70irTZ2EHIK0PWqr SHQPBlDqquTzWGUwx7aKVe6+Qg3z7swTt/8MsoGJPmbrXeLyURBJ4yZfNa73jIZvtvK+dspFZds GSBx9EeWD6yOqKbXmryWFHRFW2jYrRvPe3XRSam/SCBdsumLN4U/d86LqsuG5jkGgqaEb2e+fF0 OxvhrYcLN/fYJr6KLSKHldYcavfD4+KYa1g+ZjWaVKAfbq4InX+0b01XJfbJE7jsHCunz4vs5+I e3VUzKDcIFLRiylqe936EXc6CCbaiBLZLwzAj7yUIBNGgwgnzVwhGNSEq/nBoPP14Y281DzMgNu Pd2HeKuOjHQjXvA8Pk9Tlj3vHOfF+4+JcjCIgnpK6ZmJrBh5HPPEDRs4M8+19JA4iUyXk4LP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-30_05,2025-05-30_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 bulkscore=0 clxscore=1015 lowpriorityscore=0 adultscore=0 priorityscore=1501 mlxscore=0 phishscore=0 spamscore=0 suspectscore=0 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505300116 Video PLLs on SM8450/SM8475 require both MMCX and MXC rails to be kept ON to configure the PLLs properly. Hence move runtime power management, PLL configuration and enable critical clocks to qcom_cc_really_probe() which ensures all required power domains are in enabled state before configuring the PLLs or enabling the clocks. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Jagadeesh Kona --- drivers/clk/qcom/videocc-sm8450.c | 58 +++++++++++++++++------------------= ---- 1 file changed, 25 insertions(+), 33 deletions(-) diff --git a/drivers/clk/qcom/videocc-sm8450.c b/drivers/clk/qcom/videocc-s= m8450.c index 2e11dcffb6646d47b298c27ef68635a465dd728e..d53182f001262324d8f54b0c6a5= e73541eb32190 100644 --- a/drivers/clk/qcom/videocc-sm8450.c +++ b/drivers/clk/qcom/videocc-sm8450.c @@ -7,7 +7,6 @@ #include #include #include -#include #include =20 #include @@ -63,6 +62,7 @@ static const struct alpha_pll_config sm8475_video_cc_pll0= _config =3D { =20 static struct clk_alpha_pll video_cc_pll0 =3D { .offset =3D 0x0, + .config =3D &video_cc_pll0_config, .vco_table =3D lucid_evo_vco, .num_vco =3D ARRAY_SIZE(lucid_evo_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], @@ -106,6 +106,7 @@ static const struct alpha_pll_config sm8475_video_cc_pl= l1_config =3D { =20 static struct clk_alpha_pll video_cc_pll1 =3D { .offset =3D 0x1000, + .config =3D &video_cc_pll1_config, .vco_table =3D lucid_evo_vco, .num_vco =3D ARRAY_SIZE(lucid_evo_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], @@ -407,6 +408,17 @@ static const struct qcom_reset_map video_cc_sm8450_res= ets[] =3D { [VIDEO_CC_MVS1C_CLK_ARES] =3D { .reg =3D 0x808c, .bit =3D 2, .udelay =3D = 1000 }, }; =20 +static struct clk_alpha_pll *video_cc_sm8450_plls[] =3D { + &video_cc_pll0, + &video_cc_pll1, +}; + +static u32 video_cc_sm8450_critical_cbcrs[] =3D { + 0x80e4, /* VIDEO_CC_AHB_CLK */ + 0x8114, /* VIDEO_CC_XO_CLK */ + 0x8130, /* VIDEO_CC_SLEEP_CLK */ +}; + static const struct regmap_config video_cc_sm8450_regmap_config =3D { .reg_bits =3D 32, .reg_stride =3D 4, @@ -415,6 +427,13 @@ static const struct regmap_config video_cc_sm8450_regm= ap_config =3D { .fast_io =3D true, }; =20 +static struct qcom_cc_driver_data video_cc_sm8450_driver_data =3D { + .alpha_plls =3D video_cc_sm8450_plls, + .num_alpha_plls =3D ARRAY_SIZE(video_cc_sm8450_plls), + .clk_cbcrs =3D video_cc_sm8450_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(video_cc_sm8450_critical_cbcrs), +}; + static const struct qcom_cc_desc video_cc_sm8450_desc =3D { .config =3D &video_cc_sm8450_regmap_config, .clks =3D video_cc_sm8450_clocks, @@ -423,6 +442,8 @@ static const struct qcom_cc_desc video_cc_sm8450_desc = =3D { .num_resets =3D ARRAY_SIZE(video_cc_sm8450_resets), .gdscs =3D video_cc_sm8450_gdscs, .num_gdscs =3D ARRAY_SIZE(video_cc_sm8450_gdscs), + .use_rpm =3D true, + .driver_data =3D &video_cc_sm8450_driver_data, }; =20 static const struct of_device_id video_cc_sm8450_match_table[] =3D { @@ -434,23 +455,6 @@ MODULE_DEVICE_TABLE(of, video_cc_sm8450_match_table); =20 static int video_cc_sm8450_probe(struct platform_device *pdev) { - struct regmap *regmap; - int ret; - - ret =3D devm_pm_runtime_enable(&pdev->dev); - if (ret) - return ret; - - ret =3D pm_runtime_resume_and_get(&pdev->dev); - if (ret) - return ret; - - regmap =3D qcom_cc_map(pdev, &video_cc_sm8450_desc); - if (IS_ERR(regmap)) { - pm_runtime_put(&pdev->dev); - return PTR_ERR(regmap); - } - if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-videocc")) { /* Update VideoCC PLL0 */ video_cc_pll0.regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; @@ -458,23 +462,11 @@ static int video_cc_sm8450_probe(struct platform_devi= ce *pdev) /* Update VideoCC PLL1 */ video_cc_pll1.regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; =20 - clk_lucid_ole_pll_configure(&video_cc_pll0, regmap, &sm8475_video_cc_pll= 0_config); - clk_lucid_ole_pll_configure(&video_cc_pll1, regmap, &sm8475_video_cc_pll= 1_config); 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Fri, 30 May 2025 13:21:49 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 54UDLmQd011666 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 30 May 2025 13:21:48 GMT Received: from [10.213.98.28] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 30 May 2025 06:21:42 -0700 From: Jagadeesh Kona Date: Fri, 30 May 2025 18:50:53 +0530 Subject: [PATCH v5 08/18] clk: qcom: videocc-sm8550: Move PLL & clk configuration to really probe Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250530-videocc-pll-multi-pd-voting-v5-8-02303b3a582d@quicinc.com> References: <20250530-videocc-pll-multi-pd-voting-v5-0-02303b3a582d@quicinc.com> In-Reply-To: <20250530-videocc-pll-multi-pd-voting-v5-0-02303b3a582d@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , "Vladimir Zapolskiy" , Dmitry Baryshkov CC: Ajit Pandey , Imran Shaik , Taniya Das , "Satya Priya Kakitapalli" , , , , , Krzysztof Kozlowski , Jagadeesh Kona , Bryan O'Donoghue , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: j6O3p5I6-6kHMEDqgLnea8yj3giaI9bv X-Proofpoint-ORIG-GUID: j6O3p5I6-6kHMEDqgLnea8yj3giaI9bv X-Authority-Analysis: v=2.4 cv=X8pSKHTe c=1 sm=1 tr=0 ts=6839b0ed cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=_rNCp6tuKEiaMLwTQYUA:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTMwMDExNiBTYWx0ZWRfX+5G4ZGfOs431 pj8lL7C2CybN+8q8JW6LcBZ9m5hdNqevz9I8/Bpf4o5V9i5rkhMHpXzpP+5Gn9/Dyz9gTCDcCdf 6ZkmirV0G2qdX0rHq5+lH9MBCp/+HRX6qap64wp2cfAGimoLW4HWPJkwshdccukCD5pFNze1+3r RVSsjSTtR8pIEsqj5tDyZTDCZcwZIcbQA3Qq8FYdLliocad+RalV3iiXjGD1zp9hKy2gEbVCHPz ACMAP5nhw2eg8bbqzXCO9RXzjpiohHz+2jhVkcz3Llm9PI4nZmchEi6VGea3rHjYsbWxI5TK3gq ZBPDtMpeEOw3tBE9CR3EJSb4dMIZYTl2fBZ7fN+tHMcMA+rVaGg7WEB8E3RSeksaB0MPTK5zTNE 3DhY34viFI6dNzRJBhASvZwukSB5nfgCzhfxBbA8NzVxLrxxoB2q3/wufN9G1Hc67ApcNqxt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-30_05,2025-05-30_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 lowpriorityscore=0 phishscore=0 spamscore=0 adultscore=0 impostorscore=0 bulkscore=0 mlxlogscore=999 suspectscore=0 clxscore=1015 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505300116 Video PLLs on SM8550/SM8650 require both MMCX and MXC rails to be kept ON to configure the PLLs properly. Hence move runtime power management, PLL configuration and enable critical clocks to qcom_cc_really_probe() which ensures all required power domains are in enabled state before configuring the PLLs or enabling the clocks. Reviewed-by: Dmitry Baryshkov Signed-off-by: Jagadeesh Kona Reviewed-by: Bryan O'Donoghue Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/videocc-sm8550.c | 66 +++++++++++++++++++----------------= ---- 1 file changed, 33 insertions(+), 33 deletions(-) diff --git a/drivers/clk/qcom/videocc-sm8550.c b/drivers/clk/qcom/videocc-s= m8550.c index fcfe0cade6d0a95e749aabbc2af1174e5a70f0db..3e5891b43ee404edc6c99bbf8f2= 583cb44df9e37 100644 --- a/drivers/clk/qcom/videocc-sm8550.c +++ b/drivers/clk/qcom/videocc-sm8550.c @@ -7,7 +7,6 @@ #include #include #include -#include #include =20 #include @@ -51,6 +50,7 @@ static struct alpha_pll_config video_cc_pll0_config =3D { =20 static struct clk_alpha_pll video_cc_pll0 =3D { .offset =3D 0x0, + .config =3D &video_cc_pll0_config, .vco_table =3D lucid_ole_vco, .num_vco =3D ARRAY_SIZE(lucid_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -82,6 +82,7 @@ static struct alpha_pll_config video_cc_pll1_config =3D { =20 static struct clk_alpha_pll video_cc_pll1 =3D { .offset =3D 0x1000, + .config =3D &video_cc_pll1_config, .vco_table =3D lucid_ole_vco, .num_vco =3D ARRAY_SIZE(lucid_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -511,6 +512,23 @@ static const struct qcom_reset_map video_cc_sm8550_res= ets[] =3D { [VIDEO_CC_XO_CLK_ARES] =3D { .reg =3D 0x8124, .bit =3D 2, .udelay =3D 100= }, }; =20 +static struct clk_alpha_pll *video_cc_sm8550_plls[] =3D { + &video_cc_pll0, + &video_cc_pll1, +}; + +static u32 video_cc_sm8550_critical_cbcrs[] =3D { + 0x80f4, /* VIDEO_CC_AHB_CLK */ + 0x8124, /* VIDEO_CC_XO_CLK */ + 0x8140, /* VIDEO_CC_SLEEP_CLK */ +}; + +static u32 video_cc_sm8650_critical_cbcrs[] =3D { + 0x80f4, /* VIDEO_CC_AHB_CLK */ + 0x8124, /* VIDEO_CC_XO_CLK */ + 0x8150, /* VIDEO_CC_SLEEP_CLK */ +}; + static const struct regmap_config video_cc_sm8550_regmap_config =3D { .reg_bits =3D 32, .reg_stride =3D 4, @@ -519,6 +537,13 @@ static const struct regmap_config video_cc_sm8550_regm= ap_config =3D { .fast_io =3D true, }; =20 +static struct qcom_cc_driver_data video_cc_sm8550_driver_data =3D { + .alpha_plls =3D video_cc_sm8550_plls, + .num_alpha_plls =3D ARRAY_SIZE(video_cc_sm8550_plls), + .clk_cbcrs =3D video_cc_sm8550_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(video_cc_sm8550_critical_cbcrs), +}; + static const struct qcom_cc_desc video_cc_sm8550_desc =3D { .config =3D &video_cc_sm8550_regmap_config, .clks =3D video_cc_sm8550_clocks, @@ -527,6 +552,8 @@ static const struct qcom_cc_desc video_cc_sm8550_desc = =3D { .num_resets =3D ARRAY_SIZE(video_cc_sm8550_resets), .gdscs =3D video_cc_sm8550_gdscs, .num_gdscs =3D ARRAY_SIZE(video_cc_sm8550_gdscs), + .use_rpm =3D true, + .driver_data =3D &video_cc_sm8550_driver_data, }; =20 static const struct of_device_id video_cc_sm8550_match_table[] =3D { @@ -538,26 +565,7 @@ MODULE_DEVICE_TABLE(of, video_cc_sm8550_match_table); =20 static int video_cc_sm8550_probe(struct platform_device *pdev) { - struct regmap *regmap; - int ret; - u32 sleep_clk_offset =3D 0x8140; - - ret =3D devm_pm_runtime_enable(&pdev->dev); - if (ret) - return ret; - - ret =3D pm_runtime_resume_and_get(&pdev->dev); - if (ret) - return ret; - - regmap =3D qcom_cc_map(pdev, &video_cc_sm8550_desc); - if (IS_ERR(regmap)) { - pm_runtime_put(&pdev->dev); - return PTR_ERR(regmap); - } - if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8650-videocc")) { - sleep_clk_offset =3D 0x8150; video_cc_pll0_config.l =3D 0x1e; video_cc_pll0_config.alpha =3D 0xa000; video_cc_pll1_config.l =3D 0x2b; @@ -569,21 +577,13 @@ static int video_cc_sm8550_probe(struct platform_devi= ce *pdev) video_cc_sm8550_clocks[VIDEO_CC_MVS1_SHIFT_CLK] =3D &video_cc_mvs1_shift= _clk.clkr; video_cc_sm8550_clocks[VIDEO_CC_MVS1C_SHIFT_CLK] =3D &video_cc_mvs1c_shi= ft_clk.clkr; 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Hence move runtime power management, PLL configuration and enable critical clocks to qcom_cc_really_probe() which ensures all required power domains are in enabled state before configuring the PLLs or enabling the clocks. This change also removes the modelling for cam_cc_gdsc_clk and keeps it always ON from probe since using CLK_IS_CRITICAL will prevent the clock controller associated power domains from collapsing due to clock framework invoking clk_pm_runtime_get() during prepare. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Jagadeesh Kona Reviewed-by: Bryan O'Donoghue --- drivers/clk/qcom/camcc-sm8450.c | 89 ++++++++++++++++++++-----------------= ---- 1 file changed, 44 insertions(+), 45 deletions(-) diff --git a/drivers/clk/qcom/camcc-sm8450.c b/drivers/clk/qcom/camcc-sm845= 0.c index 08982737e4901c0703e19f8dd2d302e24748210c..4dd8be8cc9881c890d2e7c3a12f= 12816a9ab47dc 100644 --- a/drivers/clk/qcom/camcc-sm8450.c +++ b/drivers/clk/qcom/camcc-sm8450.c @@ -86,6 +86,7 @@ static const struct alpha_pll_config sm8475_cam_cc_pll0_c= onfig =3D { =20 static struct clk_alpha_pll cam_cc_pll0 =3D { .offset =3D 0x0, + .config =3D &cam_cc_pll0_config, .vco_table =3D lucid_evo_vco, .num_vco =3D ARRAY_SIZE(lucid_evo_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], @@ -191,6 +192,7 @@ static const struct alpha_pll_config sm8475_cam_cc_pll1= _config =3D { =20 static struct clk_alpha_pll cam_cc_pll1 =3D { .offset =3D 0x1000, + .config =3D &cam_cc_pll1_config, .vco_table =3D lucid_evo_vco, .num_vco =3D ARRAY_SIZE(lucid_evo_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], @@ -257,6 +259,7 @@ static const struct alpha_pll_config sm8475_cam_cc_pll2= _config =3D { =20 static struct clk_alpha_pll cam_cc_pll2 =3D { .offset =3D 0x2000, + .config =3D &cam_cc_pll2_config, .vco_table =3D rivian_evo_vco, .num_vco =3D ARRAY_SIZE(rivian_evo_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO], @@ -296,6 +299,7 @@ static const struct alpha_pll_config sm8475_cam_cc_pll3= _config =3D { =20 static struct clk_alpha_pll cam_cc_pll3 =3D { .offset =3D 0x3000, + .config =3D &cam_cc_pll3_config, .vco_table =3D lucid_evo_vco, .num_vco =3D ARRAY_SIZE(lucid_evo_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], @@ -368,6 +372,7 @@ static const struct alpha_pll_config sm8475_cam_cc_pll4= _config =3D { =20 static struct clk_alpha_pll cam_cc_pll4 =3D { .offset =3D 0x4000, + .config =3D &cam_cc_pll4_config, .vco_table =3D lucid_evo_vco, .num_vco =3D ARRAY_SIZE(lucid_evo_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], @@ -440,6 +445,7 @@ static const struct alpha_pll_config sm8475_cam_cc_pll5= _config =3D { =20 static struct clk_alpha_pll cam_cc_pll5 =3D { .offset =3D 0x5000, + .config =3D &cam_cc_pll5_config, .vco_table =3D lucid_evo_vco, .num_vco =3D ARRAY_SIZE(lucid_evo_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], @@ -512,6 +518,7 @@ static const struct alpha_pll_config sm8475_cam_cc_pll6= _config =3D { =20 static struct clk_alpha_pll cam_cc_pll6 =3D { .offset =3D 0x6000, + .config =3D &cam_cc_pll6_config, .vco_table =3D lucid_evo_vco, .num_vco =3D ARRAY_SIZE(lucid_evo_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], @@ -584,6 +591,7 @@ static const struct alpha_pll_config sm8475_cam_cc_pll7= _config =3D { =20 static struct clk_alpha_pll cam_cc_pll7 =3D { .offset =3D 0x7000, + .config =3D &cam_cc_pll7_config, .vco_table =3D lucid_evo_vco, .num_vco =3D ARRAY_SIZE(lucid_evo_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], @@ -656,6 +664,7 @@ static const struct alpha_pll_config sm8475_cam_cc_pll8= _config =3D { =20 static struct clk_alpha_pll cam_cc_pll8 =3D { .offset =3D 0x8000, + .config =3D &cam_cc_pll8_config, .vco_table =3D lucid_evo_vco, .num_vco =3D ARRAY_SIZE(lucid_evo_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], @@ -1476,24 +1485,6 @@ static struct clk_rcg2 cam_cc_xo_clk_src =3D { }, }; =20 -static struct clk_branch cam_cc_gdsc_clk =3D { - .halt_reg =3D 0x1320c, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x1320c, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "cam_cc_gdsc_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &cam_cc_xo_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - static struct clk_branch cam_cc_bps_ahb_clk =3D { .halt_reg =3D 0x1004c, .halt_check =3D BRANCH_HALT, @@ -2819,7 +2810,6 @@ static struct clk_regmap *cam_cc_sm8450_clocks[] =3D { [CAM_CC_CSIPHY4_CLK] =3D &cam_cc_csiphy4_clk.clkr, [CAM_CC_CSIPHY5_CLK] =3D &cam_cc_csiphy5_clk.clkr, [CAM_CC_FAST_AHB_CLK_SRC] =3D &cam_cc_fast_ahb_clk_src.clkr, - [CAM_CC_GDSC_CLK] =3D &cam_cc_gdsc_clk.clkr, [CAM_CC_ICP_AHB_CLK] =3D &cam_cc_icp_ahb_clk.clkr, [CAM_CC_ICP_CLK] =3D &cam_cc_icp_clk.clkr, [CAM_CC_ICP_CLK_SRC] =3D &cam_cc_icp_clk_src.clkr, @@ -2913,6 +2903,22 @@ static const struct qcom_reset_map cam_cc_sm8450_res= ets[] =3D { [CAM_CC_SFE_1_BCR] =3D { 0x13094 }, }; =20 +static struct clk_alpha_pll *cam_cc_sm8450_plls[] =3D { + &cam_cc_pll0, + &cam_cc_pll1, + &cam_cc_pll2, + &cam_cc_pll3, + &cam_cc_pll4, + &cam_cc_pll5, + &cam_cc_pll6, + &cam_cc_pll7, + &cam_cc_pll8, +}; + +static u32 cam_cc_sm8450_critical_cbcrs[] =3D { + 0x1320c, /* CAM_CC_GDSC_CLK */ +}; + static const struct regmap_config cam_cc_sm8450_regmap_config =3D { .reg_bits =3D 32, .reg_stride =3D 4, @@ -3021,6 +3027,13 @@ static struct gdsc *cam_cc_sm8450_gdscs[] =3D { [TITAN_TOP_GDSC] =3D &titan_top_gdsc, }; =20 +static struct qcom_cc_driver_data cam_cc_sm8450_driver_data =3D { + .alpha_plls =3D cam_cc_sm8450_plls, + .num_alpha_plls =3D ARRAY_SIZE(cam_cc_sm8450_plls), + .clk_cbcrs =3D cam_cc_sm8450_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(cam_cc_sm8450_critical_cbcrs), +}; + static const struct qcom_cc_desc cam_cc_sm8450_desc =3D { .config =3D &cam_cc_sm8450_regmap_config, .clks =3D cam_cc_sm8450_clocks, @@ -3029,6 +3042,8 @@ static const struct qcom_cc_desc cam_cc_sm8450_desc = =3D { .num_resets =3D ARRAY_SIZE(cam_cc_sm8450_resets), .gdscs =3D cam_cc_sm8450_gdscs, .num_gdscs =3D ARRAY_SIZE(cam_cc_sm8450_gdscs), + .use_rpm =3D true, + .driver_data =3D &cam_cc_sm8450_driver_data, }; =20 static const struct of_device_id cam_cc_sm8450_match_table[] =3D { @@ -3040,12 +3055,6 @@ MODULE_DEVICE_TABLE(of, cam_cc_sm8450_match_table); =20 static int cam_cc_sm8450_probe(struct platform_device *pdev) { - struct regmap *regmap; - - regmap =3D qcom_cc_map(pdev, &cam_cc_sm8450_desc); - if (IS_ERR(regmap)) - return PTR_ERR(regmap); - if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-camcc")) { /* Update CAMCC PLL0 */ cam_cc_pll0.regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; @@ -3092,28 +3101,18 @@ static int cam_cc_sm8450_probe(struct platform_devi= ce *pdev) cam_cc_pll8_out_even.regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCI= D_OLE]; cam_cc_pll8_out_even.clkr.hw.init =3D &sm8475_cam_cc_pll8_out_even_init; =20 - clk_lucid_ole_pll_configure(&cam_cc_pll0, regmap, &sm8475_cam_cc_pll0_co= nfig); - clk_lucid_ole_pll_configure(&cam_cc_pll1, regmap, &sm8475_cam_cc_pll1_co= nfig); - clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &sm8475_cam_cc_pll2_c= onfig); - clk_lucid_ole_pll_configure(&cam_cc_pll3, regmap, &sm8475_cam_cc_pll3_co= nfig); - clk_lucid_ole_pll_configure(&cam_cc_pll4, regmap, &sm8475_cam_cc_pll4_co= nfig); - clk_lucid_ole_pll_configure(&cam_cc_pll5, regmap, &sm8475_cam_cc_pll5_co= nfig); - clk_lucid_ole_pll_configure(&cam_cc_pll6, regmap, &sm8475_cam_cc_pll6_co= nfig); - clk_lucid_ole_pll_configure(&cam_cc_pll7, regmap, &sm8475_cam_cc_pll7_co= nfig); - clk_lucid_ole_pll_configure(&cam_cc_pll8, regmap, &sm8475_cam_cc_pll8_co= nfig); - } else { - clk_lucid_evo_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); - clk_lucid_evo_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config); - clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); - clk_lucid_evo_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config); - clk_lucid_evo_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config); - clk_lucid_evo_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config); - clk_lucid_evo_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config); 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Hence move runtime power management, PLL configuration and enabling critical clocks to qcom_cc_really_probe() which ensures all required power domains are in enabled state before configuring the PLLs or enabling the clocks. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Jagadeesh Kona Reviewed-by: Bryan O'Donoghue --- drivers/clk/qcom/camcc-sm8550.c | 85 +++++++++++++++++++++----------------= ---- 1 file changed, 44 insertions(+), 41 deletions(-) diff --git a/drivers/clk/qcom/camcc-sm8550.c b/drivers/clk/qcom/camcc-sm855= 0.c index 871155783c798fd9245d735642272eae2a2d3465..63aed9e4c362d523093409f74ef= 4e57f292ddf90 100644 --- a/drivers/clk/qcom/camcc-sm8550.c +++ b/drivers/clk/qcom/camcc-sm8550.c @@ -7,7 +7,6 @@ #include #include #include -#include #include =20 #include @@ -74,6 +73,7 @@ static const struct alpha_pll_config cam_cc_pll0_config = =3D { =20 static struct clk_alpha_pll cam_cc_pll0 =3D { .offset =3D 0x0, + .config =3D &cam_cc_pll0_config, .vco_table =3D lucid_ole_vco, .num_vco =3D ARRAY_SIZE(lucid_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -151,6 +151,7 @@ static const struct alpha_pll_config cam_cc_pll1_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll1 =3D { .offset =3D 0x1000, + .config =3D &cam_cc_pll1_config, .vco_table =3D lucid_ole_vco, .num_vco =3D ARRAY_SIZE(lucid_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -201,6 +202,7 @@ static const struct alpha_pll_config cam_cc_pll2_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll2 =3D { .offset =3D 0x2000, + .config =3D &cam_cc_pll2_config, .vco_table =3D rivian_ole_vco, .num_vco =3D ARRAY_SIZE(rivian_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO], @@ -232,6 +234,7 @@ static const struct alpha_pll_config cam_cc_pll3_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll3 =3D { .offset =3D 0x3000, + .config =3D &cam_cc_pll3_config, .vco_table =3D lucid_ole_vco, .num_vco =3D ARRAY_SIZE(lucid_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -286,6 +289,7 @@ static const struct alpha_pll_config cam_cc_pll4_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll4 =3D { .offset =3D 0x4000, + .config =3D &cam_cc_pll4_config, .vco_table =3D lucid_ole_vco, .num_vco =3D ARRAY_SIZE(lucid_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -340,6 +344,7 @@ static const struct alpha_pll_config cam_cc_pll5_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll5 =3D { .offset =3D 0x5000, + .config =3D &cam_cc_pll5_config, .vco_table =3D lucid_ole_vco, .num_vco =3D ARRAY_SIZE(lucid_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -394,6 +399,7 @@ static const struct alpha_pll_config cam_cc_pll6_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll6 =3D { .offset =3D 0x6000, + .config =3D &cam_cc_pll6_config, .vco_table =3D lucid_ole_vco, .num_vco =3D ARRAY_SIZE(lucid_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -448,6 +454,7 @@ static const struct alpha_pll_config cam_cc_pll7_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll7 =3D { .offset =3D 0x7000, + .config =3D &cam_cc_pll7_config, .vco_table =3D lucid_ole_vco, .num_vco =3D ARRAY_SIZE(lucid_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -502,6 +509,7 @@ static const struct alpha_pll_config cam_cc_pll8_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll8 =3D { .offset =3D 0x8000, + .config =3D &cam_cc_pll8_config, .vco_table =3D lucid_ole_vco, .num_vco =3D ARRAY_SIZE(lucid_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -556,6 +564,7 @@ static const struct alpha_pll_config cam_cc_pll9_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll9 =3D { .offset =3D 0x9000, + .config =3D &cam_cc_pll9_config, .vco_table =3D lucid_ole_vco, .num_vco =3D ARRAY_SIZE(lucid_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -610,6 +619,7 @@ static const struct alpha_pll_config cam_cc_pll10_confi= g =3D { =20 static struct clk_alpha_pll cam_cc_pll10 =3D { .offset =3D 0xa000, + .config =3D &cam_cc_pll10_config, .vco_table =3D lucid_ole_vco, .num_vco =3D ARRAY_SIZE(lucid_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -664,6 +674,7 @@ static const struct alpha_pll_config cam_cc_pll11_confi= g =3D { =20 static struct clk_alpha_pll cam_cc_pll11 =3D { .offset =3D 0xb000, + .config =3D &cam_cc_pll11_config, .vco_table =3D lucid_ole_vco, .num_vco =3D ARRAY_SIZE(lucid_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -718,6 +729,7 @@ static const struct alpha_pll_config cam_cc_pll12_confi= g =3D { =20 static struct clk_alpha_pll cam_cc_pll12 =3D { .offset =3D 0xc000, + .config =3D &cam_cc_pll12_config, .vco_table =3D lucid_ole_vco, .num_vco =3D ARRAY_SIZE(lucid_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -3479,6 +3491,27 @@ static const struct qcom_reset_map cam_cc_sm8550_res= ets[] =3D { [CAM_CC_SFE_1_BCR] =3D { 0x133dc }, }; =20 +static struct clk_alpha_pll *cam_cc_sm8550_plls[] =3D { + &cam_cc_pll0, + &cam_cc_pll1, + &cam_cc_pll2, + &cam_cc_pll3, + &cam_cc_pll4, + &cam_cc_pll5, + &cam_cc_pll6, + &cam_cc_pll7, + &cam_cc_pll8, + &cam_cc_pll9, + &cam_cc_pll10, + &cam_cc_pll11, + &cam_cc_pll12, +}; + +static u32 cam_cc_sm8550_critical_cbcrs[] =3D { + 0x1419c, /* CAM_CC_GDSC_CLK */ + 0x142cc, /* CAM_CC_SLEEP_CLK */ +}; + static const struct regmap_config cam_cc_sm8550_regmap_config =3D { .reg_bits =3D 32, .reg_stride =3D 4, @@ -3487,6 +3520,13 @@ static const struct regmap_config cam_cc_sm8550_regm= ap_config =3D { .fast_io =3D true, }; =20 +static struct qcom_cc_driver_data cam_cc_sm8550_driver_data =3D { + .alpha_plls =3D cam_cc_sm8550_plls, + .num_alpha_plls =3D ARRAY_SIZE(cam_cc_sm8550_plls), + .clk_cbcrs =3D cam_cc_sm8550_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(cam_cc_sm8550_critical_cbcrs), +}; + static const struct qcom_cc_desc cam_cc_sm8550_desc =3D { .config =3D &cam_cc_sm8550_regmap_config, .clks =3D cam_cc_sm8550_clocks, @@ -3495,6 +3535,8 @@ static const struct qcom_cc_desc cam_cc_sm8550_desc = =3D { .num_resets =3D ARRAY_SIZE(cam_cc_sm8550_resets), .gdscs =3D cam_cc_sm8550_gdscs, .num_gdscs =3D ARRAY_SIZE(cam_cc_sm8550_gdscs), + .use_rpm =3D true, + .driver_data =3D &cam_cc_sm8550_driver_data, }; =20 static const struct of_device_id cam_cc_sm8550_match_table[] =3D { @@ -3505,46 +3547,7 @@ MODULE_DEVICE_TABLE(of, cam_cc_sm8550_match_table); =20 static int cam_cc_sm8550_probe(struct platform_device *pdev) { - struct regmap *regmap; - int ret; - - ret =3D devm_pm_runtime_enable(&pdev->dev); - if (ret) - return ret; - - ret =3D pm_runtime_resume_and_get(&pdev->dev); - if (ret) - return ret; - - regmap =3D qcom_cc_map(pdev, &cam_cc_sm8550_desc); - if (IS_ERR(regmap)) { - pm_runtime_put(&pdev->dev); - return PTR_ERR(regmap); - } - - clk_lucid_ole_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); - clk_lucid_ole_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config); - clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); - clk_lucid_ole_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config); - clk_lucid_ole_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config); - clk_lucid_ole_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config); - clk_lucid_ole_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config); 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Fri, 30 May 2025 13:22:07 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 54UDM60E015866 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 30 May 2025 13:22:06 GMT Received: from [10.213.98.28] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 30 May 2025 06:22:00 -0700 From: Jagadeesh Kona Date: Fri, 30 May 2025 18:50:56 +0530 Subject: [PATCH v5 11/18] clk: qcom: camcc-sm8650: Move PLL & clk configuration to really probe Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250530-videocc-pll-multi-pd-voting-v5-11-02303b3a582d@quicinc.com> References: <20250530-videocc-pll-multi-pd-voting-v5-0-02303b3a582d@quicinc.com> In-Reply-To: <20250530-videocc-pll-multi-pd-voting-v5-0-02303b3a582d@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , "Vladimir Zapolskiy" , Dmitry Baryshkov CC: Ajit Pandey , Imran Shaik , Taniya Das , "Satya Priya Kakitapalli" , , , , , Krzysztof Kozlowski , Jagadeesh Kona , Bryan O'Donoghue , Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTMwMDExNiBTYWx0ZWRfX4BvRZ7KXu2Vz uYwlLf/y1g61sylWWytQJdeyQoA/9bP5rDFCB33Ey3b7+KBI54bdqneY3OP49tWbjoQf3FFTaVb m3IGJRUDsYCAqqjA0JLZ3J8ww0rN/YMblsHCy7gYwGSQGTKSi+qUqtBQ5Tu8le9MeNyaNA5YUxh V4uxxrpuDzHZEK9qA3vcQhA2Rd6dDfFzE3QV8F+v4E/qTBsHpWMkoCWT+j55nVwXWeQ1IahvXC1 +WEmgxqjV5w2O8FDSgqk484ElvIRmXVnZkpIrEvuOl/VULyxq3PsTEQRlJrWZCjq3oNXvZMHoZf 7GK8/s8qcZhz6IQlBYKKsrSQiFMo6WoeM2P/H8tR+5ncsijp6W0e65bf+R8AHSahTXofbz4UjKx wN0FvmifxvlXRGAKGM+QnWmkGOmhDwOWYcfcPrSfDqzz2QGGleClRw2mC718BlSJtivyjHRd X-Authority-Analysis: v=2.4 cv=EfHIQOmC c=1 sm=1 tr=0 ts=6839b0ff cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=s2paB303WvPZy8Ug-xUA:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: B1InAR2O-SzLFYvP3UvP4Tza0VPVol-0 X-Proofpoint-ORIG-GUID: B1InAR2O-SzLFYvP3UvP4Tza0VPVol-0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-30_05,2025-05-30_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 adultscore=0 spamscore=0 lowpriorityscore=0 suspectscore=0 clxscore=1015 bulkscore=0 mlxlogscore=999 mlxscore=0 malwarescore=0 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505300116 Camera PLLs on SM8650 require both MMCX and MXC rails to be kept ON to configure the PLLs properly. Hence move runtime power management, PLL configuration and enabling critical clocks to qcom_cc_really_probe() which ensures all required power domains are in enabled state before configuring the PLLs or enabling the clocks. Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Jagadeesh Kona Reviewed-by: Bryan O'Donoghue --- drivers/clk/qcom/camcc-sm8650.c | 83 +++++++++++++++++++++----------------= ---- 1 file changed, 42 insertions(+), 41 deletions(-) diff --git a/drivers/clk/qcom/camcc-sm8650.c b/drivers/clk/qcom/camcc-sm865= 0.c index 0ccd6de8ba78a3493f8f853a4330d2676b5743d4..8b388904f56fc3b3f77a43a09f7= 35ace24b9fcf7 100644 --- a/drivers/clk/qcom/camcc-sm8650.c +++ b/drivers/clk/qcom/camcc-sm8650.c @@ -7,7 +7,6 @@ #include #include #include -#include #include =20 #include @@ -72,6 +71,7 @@ static const struct alpha_pll_config cam_cc_pll0_config = =3D { =20 static struct clk_alpha_pll cam_cc_pll0 =3D { .offset =3D 0x0, + .config =3D &cam_cc_pll0_config, .vco_table =3D lucid_ole_vco, .num_vco =3D ARRAY_SIZE(lucid_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -149,6 +149,7 @@ static const struct alpha_pll_config cam_cc_pll1_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll1 =3D { .offset =3D 0x1000, + .config =3D &cam_cc_pll1_config, .vco_table =3D lucid_ole_vco, .num_vco =3D ARRAY_SIZE(lucid_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -199,6 +200,7 @@ static const struct alpha_pll_config cam_cc_pll2_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll2 =3D { .offset =3D 0x2000, + .config =3D &cam_cc_pll2_config, .vco_table =3D rivian_ole_vco, .num_vco =3D ARRAY_SIZE(rivian_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO], @@ -230,6 +232,7 @@ static const struct alpha_pll_config cam_cc_pll3_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll3 =3D { .offset =3D 0x3000, + .config =3D &cam_cc_pll3_config, .vco_table =3D lucid_ole_vco, .num_vco =3D ARRAY_SIZE(lucid_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -284,6 +287,7 @@ static const struct alpha_pll_config cam_cc_pll4_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll4 =3D { .offset =3D 0x4000, + .config =3D &cam_cc_pll4_config, .vco_table =3D lucid_ole_vco, .num_vco =3D ARRAY_SIZE(lucid_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -338,6 +342,7 @@ static const struct alpha_pll_config cam_cc_pll5_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll5 =3D { .offset =3D 0x5000, + .config =3D &cam_cc_pll5_config, .vco_table =3D lucid_ole_vco, .num_vco =3D ARRAY_SIZE(lucid_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -392,6 +397,7 @@ static const struct alpha_pll_config cam_cc_pll6_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll6 =3D { .offset =3D 0x6000, + .config =3D &cam_cc_pll6_config, .vco_table =3D lucid_ole_vco, .num_vco =3D ARRAY_SIZE(lucid_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -446,6 +452,7 @@ static const struct alpha_pll_config cam_cc_pll7_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll7 =3D { .offset =3D 0x7000, + .config =3D &cam_cc_pll7_config, .vco_table =3D lucid_ole_vco, .num_vco =3D ARRAY_SIZE(lucid_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -500,6 +507,7 @@ static const struct alpha_pll_config cam_cc_pll8_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll8 =3D { .offset =3D 0x8000, + .config =3D &cam_cc_pll8_config, .vco_table =3D lucid_ole_vco, .num_vco =3D ARRAY_SIZE(lucid_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -554,6 +562,7 @@ static const struct alpha_pll_config cam_cc_pll9_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll9 =3D { .offset =3D 0x9000, + .config =3D &cam_cc_pll9_config, .vco_table =3D lucid_ole_vco, .num_vco =3D ARRAY_SIZE(lucid_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -631,6 +640,7 @@ static const struct alpha_pll_config cam_cc_pll10_confi= g =3D { =20 static struct clk_alpha_pll cam_cc_pll10 =3D { .offset =3D 0xa000, + .config =3D &cam_cc_pll10_config, .vco_table =3D lucid_ole_vco, .num_vco =3D ARRAY_SIZE(lucid_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -3509,6 +3519,27 @@ static const struct qcom_reset_map cam_cc_sm8650_res= ets[] =3D { [CAM_CC_SFE_2_BCR] =3D { 0x130f4 }, }; =20 +static struct clk_alpha_pll *cam_cc_sm8650_plls[] =3D { + &cam_cc_pll0, + &cam_cc_pll1, + &cam_cc_pll2, + &cam_cc_pll3, + &cam_cc_pll4, + &cam_cc_pll5, + &cam_cc_pll6, + &cam_cc_pll7, + &cam_cc_pll8, + &cam_cc_pll9, + &cam_cc_pll10, +}; + +static u32 cam_cc_sm8650_critical_cbcrs[] =3D { + 0x132ec, /* CAM_CC_GDSC_CLK */ + 0x13308, /* CAM_CC_SLEEP_CLK */ + 0x13314, /* CAM_CC_DRV_XO_CLK */ + 0x13318, /* CAM_CC_DRV_AHB_CLK */ +}; + static const struct regmap_config cam_cc_sm8650_regmap_config =3D { .reg_bits =3D 32, .reg_stride =3D 4, @@ -3517,6 +3548,13 @@ static const struct regmap_config cam_cc_sm8650_regm= ap_config =3D { .fast_io =3D true, }; =20 +static struct qcom_cc_driver_data cam_cc_sm8650_driver_data =3D { + .alpha_plls =3D cam_cc_sm8650_plls, + .num_alpha_plls =3D ARRAY_SIZE(cam_cc_sm8650_plls), + .clk_cbcrs =3D cam_cc_sm8650_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(cam_cc_sm8650_critical_cbcrs), +}; + static const struct qcom_cc_desc cam_cc_sm8650_desc =3D { .config =3D &cam_cc_sm8650_regmap_config, .clks =3D cam_cc_sm8650_clocks, @@ -3525,6 +3563,8 @@ static const struct qcom_cc_desc cam_cc_sm8650_desc = =3D { .num_resets =3D ARRAY_SIZE(cam_cc_sm8650_resets), .gdscs =3D cam_cc_sm8650_gdscs, .num_gdscs =3D ARRAY_SIZE(cam_cc_sm8650_gdscs), + .use_rpm =3D true, + .driver_data =3D &cam_cc_sm8650_driver_data, }; =20 static const struct of_device_id cam_cc_sm8650_match_table[] =3D { @@ -3535,46 +3575,7 @@ MODULE_DEVICE_TABLE(of, cam_cc_sm8650_match_table); =20 static int cam_cc_sm8650_probe(struct platform_device *pdev) { - struct regmap *regmap; - int ret; - - ret =3D devm_pm_runtime_enable(&pdev->dev); - if (ret) - return ret; - - ret =3D pm_runtime_resume_and_get(&pdev->dev); - if (ret) - return ret; - - regmap =3D qcom_cc_map(pdev, &cam_cc_sm8650_desc); - if (IS_ERR(regmap)) { - pm_runtime_put(&pdev->dev); - return PTR_ERR(regmap); - } - - clk_lucid_ole_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); - clk_lucid_ole_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config); - clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); - clk_lucid_ole_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config); - clk_lucid_ole_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config); - clk_lucid_ole_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config); - clk_lucid_ole_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config); 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Fri, 30 May 2025 13:22:13 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 54UDMCrI015989 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 30 May 2025 13:22:12 GMT Received: from [10.213.98.28] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 30 May 2025 06:22:06 -0700 From: Jagadeesh Kona Date: Fri, 30 May 2025 18:50:57 +0530 Subject: [PATCH v5 12/18] clk: qcom: camcc-x1e80100: Move PLL & clk configuration to really probe Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250530-videocc-pll-multi-pd-voting-v5-12-02303b3a582d@quicinc.com> References: <20250530-videocc-pll-multi-pd-voting-v5-0-02303b3a582d@quicinc.com> In-Reply-To: <20250530-videocc-pll-multi-pd-voting-v5-0-02303b3a582d@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , "Vladimir Zapolskiy" , Dmitry Baryshkov CC: Ajit Pandey , Imran Shaik , Taniya Das , "Satya Priya Kakitapalli" , , , , , Krzysztof Kozlowski , Jagadeesh Kona , Bryan O'Donoghue , Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: _gRiCBBgO-8FGM_iq4lt5_UWwnfn_T2E X-Proofpoint-ORIG-GUID: _gRiCBBgO-8FGM_iq4lt5_UWwnfn_T2E X-Authority-Analysis: v=2.4 cv=X8FSKHTe c=1 sm=1 tr=0 ts=6839b105 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=ytWGrkJ68uyaVPSImB0A:9 a=QEXdDO2ut3YA:10 a=cvBusfyB2V15izCimMoJ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTMwMDExNiBTYWx0ZWRfX9y3fjOX15W7+ oxGhsBQ3BYjQh6x7qnouuAyHOisXDf6OLWYNl5bQL/eP2DHcB69HKDtpRPcFstSPe35T5X5fwc/ 2EVYunzfpqm/lhgJYYE4FbKWM8UkB2r2biOlAQg+splZvVltrqsLLfSGs0f3PKsNB9AKXEwpde9 Err+CdhI9IZKPi1c0cZo31s10W3gjUWN1RHW5ZpGYiwMutZFLvr4hQomkPfuF6zQnldKY/fEctV wOaaZfwi5/75TGt5VKZInBBC1piH4WB6htMAau7c3RtqtYMCSq9zLUB9aUYG01MAY1N9jB9Wh8j 2Un/ONqVF5+uAymGIVQvHuyFGfiGfZOmp0Xa3lg5f+mP1bp4vi3z9Rm49SIF4o+3gv2frkK34dm cYw37inPV8KDzUMQkTF/GnO8aq8nqTlRSRFlsPvx2xCApdrCxDBioYJmkDw0iS8WlTWG6ntT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-30_05,2025-05-30_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 phishscore=0 bulkscore=0 mlxlogscore=999 mlxscore=0 clxscore=1015 priorityscore=1501 spamscore=0 adultscore=0 malwarescore=0 lowpriorityscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505300116 Camera PLLs on X1E80100 require both MMCX and MXC rails to be kept ON to configure the PLLs properly. Hence move runtime power management, PLL configuration and enabling critical clocks to qcom_cc_really_probe() which ensures all required power domains are in enabled state before configuring the PLLs or enabling the clocks. Reviewed-by: Bryan O'Donoghue Tested-by: Bryan O'Donoghue # Dell Inspiron Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Jagadeesh Kona --- drivers/clk/qcom/camcc-x1e80100.c | 67 +++++++++++++++++++----------------= ---- 1 file changed, 32 insertions(+), 35 deletions(-) diff --git a/drivers/clk/qcom/camcc-x1e80100.c b/drivers/clk/qcom/camcc-x1e= 80100.c index b73524ae64b1b2b1ee94ceca88b5f3b46143f20b..cbcc1c9fcb341e51272f5595f57= 4f9cb7ef2b52e 100644 --- a/drivers/clk/qcom/camcc-x1e80100.c +++ b/drivers/clk/qcom/camcc-x1e80100.c @@ -7,7 +7,6 @@ #include #include #include -#include #include =20 #include @@ -67,6 +66,7 @@ static const struct alpha_pll_config cam_cc_pll0_config = =3D { =20 static struct clk_alpha_pll cam_cc_pll0 =3D { .offset =3D 0x0, + .config =3D &cam_cc_pll0_config, .vco_table =3D lucid_ole_vco, .num_vco =3D ARRAY_SIZE(lucid_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -144,6 +144,7 @@ static const struct alpha_pll_config cam_cc_pll1_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll1 =3D { .offset =3D 0x1000, + .config =3D &cam_cc_pll1_config, .vco_table =3D lucid_ole_vco, .num_vco =3D ARRAY_SIZE(lucid_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -194,6 +195,7 @@ static const struct alpha_pll_config cam_cc_pll2_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll2 =3D { .offset =3D 0x2000, + .config =3D &cam_cc_pll2_config, .vco_table =3D rivian_ole_vco, .num_vco =3D ARRAY_SIZE(rivian_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO], @@ -225,6 +227,7 @@ static const struct alpha_pll_config cam_cc_pll3_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll3 =3D { .offset =3D 0x3000, + .config =3D &cam_cc_pll3_config, .vco_table =3D lucid_ole_vco, .num_vco =3D ARRAY_SIZE(lucid_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -279,6 +282,7 @@ static const struct alpha_pll_config cam_cc_pll4_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll4 =3D { .offset =3D 0x4000, + .config =3D &cam_cc_pll4_config, .vco_table =3D lucid_ole_vco, .num_vco =3D ARRAY_SIZE(lucid_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -333,6 +337,7 @@ static const struct alpha_pll_config cam_cc_pll6_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll6 =3D { .offset =3D 0x6000, + .config =3D &cam_cc_pll6_config, .vco_table =3D lucid_ole_vco, .num_vco =3D ARRAY_SIZE(lucid_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -387,6 +392,7 @@ static const struct alpha_pll_config cam_cc_pll8_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll8 =3D { .offset =3D 0x8000, + .config =3D &cam_cc_pll8_config, .vco_table =3D lucid_ole_vco, .num_vco =3D ARRAY_SIZE(lucid_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -2418,6 +2424,21 @@ static const struct qcom_reset_map cam_cc_x1e80100_r= esets[] =3D { [CAM_CC_SFE_0_BCR] =3D { 0x1327c }, }; =20 +static struct clk_alpha_pll *cam_cc_x1e80100_plls[] =3D { + &cam_cc_pll0, + &cam_cc_pll1, + &cam_cc_pll2, + &cam_cc_pll3, + &cam_cc_pll4, + &cam_cc_pll6, + &cam_cc_pll8, +}; + +static u32 cam_cc_x1e80100_critical_cbcrs[] =3D { + 0x13a9c, /* CAM_CC_GDSC_CLK */ + 0x13ab8, /* CAM_CC_SLEEP_CLK */ +}; + static const struct regmap_config cam_cc_x1e80100_regmap_config =3D { .reg_bits =3D 32, .reg_stride =3D 4, @@ -2426,6 +2447,13 @@ static const struct regmap_config cam_cc_x1e80100_re= gmap_config =3D { .fast_io =3D true, }; =20 +static struct qcom_cc_driver_data cam_cc_x1e80100_driver_data =3D { + .alpha_plls =3D cam_cc_x1e80100_plls, + .num_alpha_plls =3D ARRAY_SIZE(cam_cc_x1e80100_plls), + .clk_cbcrs =3D cam_cc_x1e80100_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(cam_cc_x1e80100_critical_cbcrs), +}; + static const struct qcom_cc_desc cam_cc_x1e80100_desc =3D { .config =3D &cam_cc_x1e80100_regmap_config, .clks =3D cam_cc_x1e80100_clocks, @@ -2434,6 +2462,8 @@ static const struct qcom_cc_desc cam_cc_x1e80100_desc= =3D { .num_resets =3D ARRAY_SIZE(cam_cc_x1e80100_resets), .gdscs =3D cam_cc_x1e80100_gdscs, .num_gdscs =3D ARRAY_SIZE(cam_cc_x1e80100_gdscs), + .use_rpm =3D true, + .driver_data =3D &cam_cc_x1e80100_driver_data, }; =20 static const struct of_device_id cam_cc_x1e80100_match_table[] =3D { @@ -2444,40 +2474,7 @@ MODULE_DEVICE_TABLE(of, cam_cc_x1e80100_match_table); =20 static int cam_cc_x1e80100_probe(struct platform_device *pdev) { - struct regmap *regmap; - int ret; - - ret =3D devm_pm_runtime_enable(&pdev->dev); - if (ret) - return ret; - - ret =3D pm_runtime_resume_and_get(&pdev->dev); - if (ret) - return ret; - - regmap =3D qcom_cc_map(pdev, &cam_cc_x1e80100_desc); - if (IS_ERR(regmap)) { - pm_runtime_put(&pdev->dev); - return PTR_ERR(regmap); - } - - clk_lucid_ole_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); - clk_lucid_ole_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config); - clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); - clk_lucid_ole_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config); - clk_lucid_ole_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config); - clk_lucid_ole_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config); - clk_lucid_ole_pll_configure(&cam_cc_pll8, regmap, &cam_cc_pll8_config); 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Fri, 30 May 2025 13:22:18 GMT Received: from [10.213.98.28] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 30 May 2025 06:22:12 -0700 From: Jagadeesh Kona Date: Fri, 30 May 2025 18:50:58 +0530 Subject: [PATCH v5 13/18] arm64: dts: qcom: sm8450: Additionally manage MXC power domain in videocc Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250530-videocc-pll-multi-pd-voting-v5-13-02303b3a582d@quicinc.com> References: <20250530-videocc-pll-multi-pd-voting-v5-0-02303b3a582d@quicinc.com> In-Reply-To: <20250530-videocc-pll-multi-pd-voting-v5-0-02303b3a582d@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , "Vladimir Zapolskiy" , Dmitry Baryshkov CC: Ajit Pandey , Imran Shaik , Taniya Das , "Satya Priya Kakitapalli" , , , , , Krzysztof Kozlowski , Jagadeesh Kona , Bryan O'Donoghue , Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: LQYSrgTjCK3a3W-thX9JOmdUNZ6i28a0 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTMwMDExNiBTYWx0ZWRfX0kN3CFur1rY1 9EkhcMnTibTrkx7kUr3/MGIC34iad9o2R54tBjpXaJI0uphmOXUT+QMAd+fHcTSJV0qLRdVwLJz W3MyEarJQRHjEZACRReVey3Yr7PgFB2W+QWh/si/WkpXaIeqxisKPpv56z1O2toxE1bO5HMVjut laBV/0ezLocA8KZRnXjmVpPsnWDXvgiR5+DynRVwqhm2mrr4BXbJhVxxtWQFDXoVtBDEZVEL2SM Sq5CUuDCF/tN3cglYHuz8M/u+6ODVS5s/eIqkt7UnF9wuHEmazI/qh6O1VoKRb6SQbNZuz7HrgD z8iM0yJ3/7y0wrOicKwQ4AFatR7vrIdGlSzUME9HYvOQoolO9kro45F++jOUoajsBrlFe9XZxXf mdyuCL/FbffngF/1cEbBVE4ZvblJg8Lmpodw0XrsI+ae3X6ySG6STi350xFp7IbhTYufo3hy X-Authority-Analysis: v=2.4 cv=fMk53Yae c=1 sm=1 tr=0 ts=6839b10b cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=yDpTXWEf0LF08gPbhRgA:9 a=QEXdDO2ut3YA:10 a=cvBusfyB2V15izCimMoJ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: LQYSrgTjCK3a3W-thX9JOmdUNZ6i28a0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-30_05,2025-05-30_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 impostorscore=0 phishscore=0 suspectscore=0 spamscore=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 mlxscore=0 mlxlogscore=572 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505300116 Videocc requires both MMCX and MXC rails to be powered ON to configure the video PLLs on SM8450 platform. Hence add MXC power domain to videocc node on SM8450. Reviewed-by: Dmitry Baryshkov Reviewed-by: Bryan O'Donoghue Reviewed-by: Konrad Dybcio Signed-off-by: Jagadeesh Kona --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qco= m/sm8450.dtsi index 0b36f4cd4497ecffe0a15cd6102e9d9ac62a7425..36a67c679fbaed944d7590528b6= 96635c306da5d 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -3198,8 +3198,10 @@ videocc: clock-controller@aaf0000 { reg =3D <0 0x0aaf0000 0 0x10000>; clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_VIDEO_AHB_CLK>; - power-domains =3D <&rpmhpd RPMHPD_MMCX>; - required-opps =3D <&rpmhpd_opp_low_svs>; + power-domains =3D <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps =3D <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; #clock-cells =3D <1>; #reset-cells =3D <1>; #power-domain-cells =3D <1>; --=20 2.34.1 From nobody Tue Dec 16 22:33:08 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B61C2232368; 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Hence add MXC power domain to videocc node on SM8550. Reviewed-by: Dmitry Baryshkov Reviewed-by: Bryan O'Donoghue Reviewed-by: Konrad Dybcio Signed-off-by: Jagadeesh Kona --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index f78d5292c5dd5ec88c8deb0ca6e5078511ac52b7..92017caedbbbea12eb2e43f2e9f= 5bcad0c0ee40c 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3225,8 +3225,10 @@ videocc: clock-controller@aaf0000 { reg =3D <0 0x0aaf0000 0 0x10000>; clocks =3D <&bi_tcxo_div2>, <&gcc GCC_VIDEO_AHB_CLK>; - power-domains =3D <&rpmhpd RPMHPD_MMCX>; - required-opps =3D <&rpmhpd_opp_low_svs>; + power-domains =3D <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps =3D <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; #clock-cells =3D <1>; #reset-cells =3D <1>; #power-domain-cells =3D <1>; --=20 2.34.1 From nobody Tue Dec 16 22:33:08 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E1592EB10; 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Hence add MXC power domain to videocc node on SM8650. Reviewed-by: Dmitry Baryshkov Reviewed-by: Bryan O'Donoghue Reviewed-by: Konrad Dybcio Signed-off-by: Jagadeesh Kona --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qco= m/sm8650.dtsi index 818db6ba3b3be99c187512ea4acf2004422f6a18..ad60596b71d25bb0198b26660dc= 41195a1210a23 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -4959,7 +4959,8 @@ videocc: clock-controller@aaf0000 { reg =3D <0 0x0aaf0000 0 0x10000>; clocks =3D <&bi_tcxo_div2>, <&gcc GCC_VIDEO_AHB_CLK>; - power-domains =3D <&rpmhpd RPMHPD_MMCX>; + power-domains =3D <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; #clock-cells =3D <1>; #reset-cells =3D <1>; #power-domain-cells =3D <1>; --=20 2.34.1 From nobody Tue Dec 16 22:33:08 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29BD42EB10; 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Hence add MXC power domain to camcc node on SM8450. Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Jagadeesh Kona Reviewed-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qco= m/sm8450.dtsi index 36a67c679fbaed944d7590528b696635c306da5d..624190c07c59f3e6714f296f1b2= 64d2a88135116 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -3292,8 +3292,10 @@ camcc: clock-controller@ade0000 { <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; - power-domains =3D <&rpmhpd RPMHPD_MMCX>; - required-opps =3D <&rpmhpd_opp_low_svs>; + power-domains =3D <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps =3D <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; #clock-cells =3D <1>; #reset-cells =3D <1>; #power-domain-cells =3D <1>; --=20 2.34.1 From nobody Tue Dec 16 22:33:08 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1C8FA1E4A4; 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Hence add MXC power domain to camcc node on SM8550. While at it, update SM8550_MMCX macro to RPMHPD_MMCX to align towards common macros. Fixes: e271b59e39a6f ("arm64: dts: qcom: sm8550: Add camera clock controlle= r") Signed-off-by: Vladimir Zapolskiy Reviewed-by: Taniya Das Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Jagadeesh Kona Reviewed-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index 92017caedbbbea12eb2e43f2e9f5bcad0c0ee40c..e9bb077aa9f0b8be28608d4a034= 5aae7df8cd167 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3333,8 +3333,10 @@ camcc: clock-controller@ade0000 { <&bi_tcxo_div2>, <&bi_tcxo_ao_div2>, <&sleep_clk>; - power-domains =3D <&rpmhpd SM8550_MMCX>; - required-opps =3D <&rpmhpd_opp_low_svs>; + power-domains =3D <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps =3D <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; #clock-cells =3D <1>; #reset-cells =3D <1>; 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Hence add MXC power domain to camcc node on SM8650. Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Jagadeesh Kona Reviewed-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qco= m/sm8650.dtsi index ad60596b71d25bb0198b26660dc41195a1210a23..a2b3d97abc7f799810e20131d72= 31608c8757859 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -5072,7 +5072,8 @@ camcc: clock-controller@ade0000 { <&bi_tcxo_div2>, <&bi_tcxo_ao_div2>, <&sleep_clk>; - power-domains =3D <&rpmhpd RPMHPD_MMCX>; + power-domains =3D <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; #clock-cells =3D <1>; #reset-cells =3D <1>; #power-domain-cells =3D <1>; --=20 2.34.1