From: Ard Biesheuvel <ardb@kernel.org>
cpu_feature_enabled() uses a ternary alternative, where the late variant
is based on code patching and the early variant accesses the capability
field in boot_cpu_data directly.
This allows cpu_feature_enabled() to be called quite early, but it still
requires that the CPU feature detection code runs before being able to
rely on the return value of cpu_feature_enabled().
This is a problem for the implementation of pgtable_l5_enabled(), which
is based on cpu_feature_enabled(X86_FEATURE_5LEVEL_PAGING), and may be
called extremely early. Currently, there is a hacky workaround where
some source files that may execute before (but also after) CPU feature
detection have a different version of pgtable_l5_enabled(), based on the
USE_EARLY_PGTABLE_L5 preprocessor macro.
Instead, let's make it possible to set CPU feature arbitrarily early, so
that the X86_FEATURE_5LEVEL_PAGING capability can be set before even
entering C code.
This involves relying on static initialization of boot_cpu_data and the
cpu_caps_set/cpu_caps_cleared arrays, so they all need to reside in
.data. This ensures that they won't be cleared along with the rest of
BSS.
Note that forcing a capability involves setting it in both
boot_cpu_data.x86_capability[] and cpu_caps_set[].
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
---
arch/x86/kernel/cpu/common.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index bbec5c4cd8ed..aaa6d9e51ef1 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -704,8 +704,8 @@ static const char *table_lookup_model(struct cpuinfo_x86 *c)
}
/* Aligned to unsigned long to avoid split lock in atomic bitmap ops */
-__u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
-__u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
+__u32 __read_mostly cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
+__u32 __read_mostly cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
#ifdef CONFIG_X86_32
/* The 32-bit entry code needs to find cpu_entry_area. */
@@ -1628,9 +1628,6 @@ static void __init cpu_parse_early_param(void)
*/
static void __init early_identify_cpu(struct cpuinfo_x86 *c)
{
- memset(&c->x86_capability, 0, sizeof(c->x86_capability));
- c->extended_cpuid_level = 0;
-
if (!have_cpuid_p())
identify_cpu_without_cpuid(c);
@@ -1842,7 +1839,8 @@ static void identify_cpu(struct cpuinfo_x86 *c)
c->x86_virt_bits = 32;
#endif
c->x86_cache_alignment = c->x86_clflush_size;
- memset(&c->x86_capability, 0, sizeof(c->x86_capability));
+ if (c != &boot_cpu_data)
+ memset(&c->x86_capability, 0, sizeof(c->x86_capability));
#ifdef CONFIG_X86_VMX_FEATURE_NAMES
memset(&c->vmx_capability, 0, sizeof(c->vmx_capability));
#endif
--
2.49.0.1045.g170613ef41-googOn Tue, May 13, 2025 at 7:40 AM Ard Biesheuvel <ardb+git@google.com> wrote:
>
> From: Ard Biesheuvel <ardb@kernel.org>
>
> cpu_feature_enabled() uses a ternary alternative, where the late variant
> is based on code patching and the early variant accesses the capability
> field in boot_cpu_data directly.
>
> This allows cpu_feature_enabled() to be called quite early, but it still
> requires that the CPU feature detection code runs before being able to
> rely on the return value of cpu_feature_enabled().
>
> This is a problem for the implementation of pgtable_l5_enabled(), which
> is based on cpu_feature_enabled(X86_FEATURE_5LEVEL_PAGING), and may be
> called extremely early. Currently, there is a hacky workaround where
> some source files that may execute before (but also after) CPU feature
> detection have a different version of pgtable_l5_enabled(), based on the
> USE_EARLY_PGTABLE_L5 preprocessor macro.
>
> Instead, let's make it possible to set CPU feature arbitrarily early, so
> that the X86_FEATURE_5LEVEL_PAGING capability can be set before even
> entering C code.
>
> This involves relying on static initialization of boot_cpu_data and the
> cpu_caps_set/cpu_caps_cleared arrays, so they all need to reside in
> .data. This ensures that they won't be cleared along with the rest of
> BSS.
>
> Note that forcing a capability involves setting it in both
> boot_cpu_data.x86_capability[] and cpu_caps_set[].
>
> Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
> ---
> arch/x86/kernel/cpu/common.c | 10 ++++------
> 1 file changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
> index bbec5c4cd8ed..aaa6d9e51ef1 100644
> --- a/arch/x86/kernel/cpu/common.c
> +++ b/arch/x86/kernel/cpu/common.c
> @@ -704,8 +704,8 @@ static const char *table_lookup_model(struct cpuinfo_x86 *c)
> }
>
> /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */
> -__u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
> -__u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
> +__u32 __read_mostly cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
> +__u32 __read_mostly cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
Is there any scenario where capabilities are changed after boot? If
not, this could possibly be __ro_after_init.
> #ifdef CONFIG_X86_32
> /* The 32-bit entry code needs to find cpu_entry_area. */
> @@ -1628,9 +1628,6 @@ static void __init cpu_parse_early_param(void)
> */
> static void __init early_identify_cpu(struct cpuinfo_x86 *c)
> {
> - memset(&c->x86_capability, 0, sizeof(c->x86_capability));
> - c->extended_cpuid_level = 0;
> -
> if (!have_cpuid_p())
> identify_cpu_without_cpuid(c);
>
> @@ -1842,7 +1839,8 @@ static void identify_cpu(struct cpuinfo_x86 *c)
> c->x86_virt_bits = 32;
> #endif
> c->x86_cache_alignment = c->x86_clflush_size;
> - memset(&c->x86_capability, 0, sizeof(c->x86_capability));
> + if (c != &boot_cpu_data)
> + memset(&c->x86_capability, 0, sizeof(c->x86_capability));
You can move the clearing of the capabilities to the caller
(identify_secondary_cpu()) instead.
Brian Gerst
On Tue, 13 May 2025 at 20:37, Brian Gerst <brgerst@gmail.com> wrote: > > On Tue, May 13, 2025 at 7:40 AM Ard Biesheuvel <ardb+git@google.com> wrote: > > > > From: Ard Biesheuvel <ardb@kernel.org> > > > > cpu_feature_enabled() uses a ternary alternative, where the late variant > > is based on code patching and the early variant accesses the capability > > field in boot_cpu_data directly. > > > > This allows cpu_feature_enabled() to be called quite early, but it still > > requires that the CPU feature detection code runs before being able to > > rely on the return value of cpu_feature_enabled(). > > > > This is a problem for the implementation of pgtable_l5_enabled(), which > > is based on cpu_feature_enabled(X86_FEATURE_5LEVEL_PAGING), and may be > > called extremely early. Currently, there is a hacky workaround where > > some source files that may execute before (but also after) CPU feature > > detection have a different version of pgtable_l5_enabled(), based on the > > USE_EARLY_PGTABLE_L5 preprocessor macro. > > > > Instead, let's make it possible to set CPU feature arbitrarily early, so > > that the X86_FEATURE_5LEVEL_PAGING capability can be set before even > > entering C code. > > > > This involves relying on static initialization of boot_cpu_data and the > > cpu_caps_set/cpu_caps_cleared arrays, so they all need to reside in > > .data. This ensures that they won't be cleared along with the rest of > > BSS. > > > > Note that forcing a capability involves setting it in both > > boot_cpu_data.x86_capability[] and cpu_caps_set[]. > > > > Signed-off-by: Ard Biesheuvel <ardb@kernel.org> > > --- > > arch/x86/kernel/cpu/common.c | 10 ++++------ > > 1 file changed, 4 insertions(+), 6 deletions(-) > > > > diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c > > index bbec5c4cd8ed..aaa6d9e51ef1 100644 > > --- a/arch/x86/kernel/cpu/common.c > > +++ b/arch/x86/kernel/cpu/common.c > > @@ -704,8 +704,8 @@ static const char *table_lookup_model(struct cpuinfo_x86 *c) > > } > > > > /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */ > > -__u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); > > -__u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); > > +__u32 __read_mostly cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); > > +__u32 __read_mostly cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); > > Is there any scenario where capabilities are changed after boot? If > not, this could possibly be __ro_after_init. > Turns out that this is not possible. https://lore.kernel.org/all/202505211627.1f9b653f-lkp@intel.com/T/#u
* Brian Gerst <brgerst@gmail.com> wrote: > On Tue, May 13, 2025 at 7:40 AM Ard Biesheuvel <ardb+git@google.com> wrote: > > > > From: Ard Biesheuvel <ardb@kernel.org> > > > > cpu_feature_enabled() uses a ternary alternative, where the late variant > > is based on code patching and the early variant accesses the capability > > field in boot_cpu_data directly. > > > > This allows cpu_feature_enabled() to be called quite early, but it still > > requires that the CPU feature detection code runs before being able to > > rely on the return value of cpu_feature_enabled(). > > > > This is a problem for the implementation of pgtable_l5_enabled(), which > > is based on cpu_feature_enabled(X86_FEATURE_5LEVEL_PAGING), and may be > > called extremely early. Currently, there is a hacky workaround where > > some source files that may execute before (but also after) CPU feature > > detection have a different version of pgtable_l5_enabled(), based on the > > USE_EARLY_PGTABLE_L5 preprocessor macro. > > > > Instead, let's make it possible to set CPU feature arbitrarily early, so > > that the X86_FEATURE_5LEVEL_PAGING capability can be set before even > > entering C code. > > > > This involves relying on static initialization of boot_cpu_data and the > > cpu_caps_set/cpu_caps_cleared arrays, so they all need to reside in > > .data. This ensures that they won't be cleared along with the rest of > > BSS. > > > > Note that forcing a capability involves setting it in both > > boot_cpu_data.x86_capability[] and cpu_caps_set[]. > > > > Signed-off-by: Ard Biesheuvel <ardb@kernel.org> > > --- > > arch/x86/kernel/cpu/common.c | 10 ++++------ > > 1 file changed, 4 insertions(+), 6 deletions(-) > > > > diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c > > index bbec5c4cd8ed..aaa6d9e51ef1 100644 > > --- a/arch/x86/kernel/cpu/common.c > > +++ b/arch/x86/kernel/cpu/common.c > > @@ -704,8 +704,8 @@ static const char *table_lookup_model(struct cpuinfo_x86 *c) > > } > > > > /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */ > > -__u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); > > -__u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); > > +__u32 __read_mostly cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); > > +__u32 __read_mostly cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); > > Is there any scenario where capabilities are changed after boot? Not supposed to... > If not, this could possibly be __ro_after_init. Yeah, and in a separate patch. Thanks, Ingo
On Wed, 14 May 2025 at 09:17, Ingo Molnar <mingo@kernel.org> wrote: > > > * Brian Gerst <brgerst@gmail.com> wrote: > > > On Tue, May 13, 2025 at 7:40 AM Ard Biesheuvel <ardb+git@google.com> wrote: > > > > > > From: Ard Biesheuvel <ardb@kernel.org> > > > > > > cpu_feature_enabled() uses a ternary alternative, where the late variant > > > is based on code patching and the early variant accesses the capability > > > field in boot_cpu_data directly. > > > > > > This allows cpu_feature_enabled() to be called quite early, but it still > > > requires that the CPU feature detection code runs before being able to > > > rely on the return value of cpu_feature_enabled(). > > > > > > This is a problem for the implementation of pgtable_l5_enabled(), which > > > is based on cpu_feature_enabled(X86_FEATURE_5LEVEL_PAGING), and may be > > > called extremely early. Currently, there is a hacky workaround where > > > some source files that may execute before (but also after) CPU feature > > > detection have a different version of pgtable_l5_enabled(), based on the > > > USE_EARLY_PGTABLE_L5 preprocessor macro. > > > > > > Instead, let's make it possible to set CPU feature arbitrarily early, so > > > that the X86_FEATURE_5LEVEL_PAGING capability can be set before even > > > entering C code. > > > > > > This involves relying on static initialization of boot_cpu_data and the > > > cpu_caps_set/cpu_caps_cleared arrays, so they all need to reside in > > > .data. This ensures that they won't be cleared along with the rest of > > > BSS. > > > > > > Note that forcing a capability involves setting it in both > > > boot_cpu_data.x86_capability[] and cpu_caps_set[]. > > > > > > Signed-off-by: Ard Biesheuvel <ardb@kernel.org> > > > --- > > > arch/x86/kernel/cpu/common.c | 10 ++++------ > > > 1 file changed, 4 insertions(+), 6 deletions(-) > > > > > > diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c > > > index bbec5c4cd8ed..aaa6d9e51ef1 100644 > > > --- a/arch/x86/kernel/cpu/common.c > > > +++ b/arch/x86/kernel/cpu/common.c > > > @@ -704,8 +704,8 @@ static const char *table_lookup_model(struct cpuinfo_x86 *c) > > > } > > > > > > /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */ > > > -__u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); > > > -__u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); > > > +__u32 __read_mostly cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); > > > +__u32 __read_mostly cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); > > > > Is there any scenario where capabilities are changed after boot? > > Not supposed to... > > > If not, this could possibly be __ro_after_init. > > Yeah, and in a separate patch. > OK.
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