The KVM virtualizes PMU in RISC-V and disables all counter access except
TM bit by default vi hstateen CSR. There is no benefit in enabling CY/TM
bits in scounteren for the guest user space as it can't be run without
hcounteren anyways.

Allow only TM bit which matches the hcounteren default setting.

Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
 arch/riscv/kvm/vcpu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index 60d684c76c58..873593bfe610 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -146,8 +146,8 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
 	if (kvm_riscv_vcpu_alloc_vector_context(vcpu, cntx))
 		return -ENOMEM;
 
-	/* By default, make CY, TM, and IR counters accessible in VU mode */
-	reset_csr->scounteren = 0x7;
+	/* By default, only TM should be accessible in VU mode */
+	reset_csr->scounteren = 0x2;
 
 	/* Setup VCPU timer */
 	kvm_riscv_vcpu_timer_init(vcpu);

---
base-commit: 01f95500a162fca88cefab9ed64ceded5afabc12
change-id: 20250513-fix_scounteren_vs-fdd86255c7b7
--
Regards,
Atish patra

On Wed, May 14, 2025 at 12:13 PM Atish Patra <atishp@rivosinc.com> wrote:
>
> The KVM virtualizes PMU in RISC-V and disables all counter access except
> TM bit by default vi hstateen CSR. There is no benefit in enabling CY/TM
> bits in scounteren for the guest user space as it can't be run without
> hcounteren anyways.
>
> Allow only TM bit which matches the hcounteren default setting.
>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> ---
>  arch/riscv/kvm/vcpu.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
> index 60d684c76c58..873593bfe610 100644
> --- a/arch/riscv/kvm/vcpu.c
> +++ b/arch/riscv/kvm/vcpu.c
> @@ -146,8 +146,8 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
>         if (kvm_riscv_vcpu_alloc_vector_context(vcpu, cntx))
>                 return -ENOMEM;
>
> -       /* By default, make CY, TM, and IR counters accessible in VU mode */
> -       reset_csr->scounteren = 0x7;
> +       /* By default, only TM should be accessible in VU mode */
> +       reset_csr->scounteren = 0x2;

Let's remove this as well because the Linux SBI PMU driver
does initialize scounteren correctly.

Regards,
Anup

On Wed, May 14, 2025 at 3:55 AM Anup Patel <anup@brainfault.org> wrote:
>
> On Wed, May 14, 2025 at 12:13 PM Atish Patra <atishp@rivosinc.com> wrote:
> >
> > The KVM virtualizes PMU in RISC-V and disables all counter access except
> > TM bit by default vi hstateen CSR. There is no benefit in enabling CY/TM
> > bits in scounteren for the guest user space as it can't be run without
> > hcounteren anyways.
> >
> > Allow only TM bit which matches the hcounteren default setting.
> >
> > Signed-off-by: Atish Patra <atishp@rivosinc.com>
> > ---
> >  arch/riscv/kvm/vcpu.c | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
> > index 60d684c76c58..873593bfe610 100644
> > --- a/arch/riscv/kvm/vcpu.c
> > +++ b/arch/riscv/kvm/vcpu.c
> > @@ -146,8 +146,8 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
> >         if (kvm_riscv_vcpu_alloc_vector_context(vcpu, cntx))
> >                 return -ENOMEM;
> >
> > -       /* By default, make CY, TM, and IR counters accessible in VU mode */
> > -       reset_csr->scounteren = 0x7;
> > +       /* By default, only TM should be accessible in VU mode */
> > +       reset_csr->scounteren = 0x2;
>
> Let's remove this as well because the Linux SBI PMU driver
> does initialize scounteren correctly.
>

But other guests may not. I thought time should be a basic one that
should be allowed by default.

>
> Regards,
> Anup

On Thu, May 15, 2025 at 2:31 AM Atish Kumar Patra <atishp@rivosinc.com> wrote:
>
> On Wed, May 14, 2025 at 3:55 AM Anup Patel <anup@brainfault.org> wrote:
> >
> > On Wed, May 14, 2025 at 12:13 PM Atish Patra <atishp@rivosinc.com> wrote:
> > >
> > > The KVM virtualizes PMU in RISC-V and disables all counter access except
> > > TM bit by default vi hstateen CSR. There is no benefit in enabling CY/TM
> > > bits in scounteren for the guest user space as it can't be run without
> > > hcounteren anyways.
> > >
> > > Allow only TM bit which matches the hcounteren default setting.
> > >
> > > Signed-off-by: Atish Patra <atishp@rivosinc.com>
> > > ---
> > >  arch/riscv/kvm/vcpu.c | 4 ++--
> > >  1 file changed, 2 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
> > > index 60d684c76c58..873593bfe610 100644
> > > --- a/arch/riscv/kvm/vcpu.c
> > > +++ b/arch/riscv/kvm/vcpu.c
> > > @@ -146,8 +146,8 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
> > >         if (kvm_riscv_vcpu_alloc_vector_context(vcpu, cntx))
> > >                 return -ENOMEM;
> > >
> > > -       /* By default, make CY, TM, and IR counters accessible in VU mode */
> > > -       reset_csr->scounteren = 0x7;
> > > +       /* By default, only TM should be accessible in VU mode */
> > > +       reset_csr->scounteren = 0x2;
> >
> > Let's remove this as well because the Linux SBI PMU driver
> > does initialize scounteren correctly.
> >
>
> But other guests may not. I thought time should be a basic one that
> should be allowed by default.
>

There is no specification (SBI or Priv spec) which mandates M-mode
or HS-mode to setup S-mode CSRs. Setting scounteren bits (including
TM bit) has always been a HACK or work-around.

It is better to remove scounteren initialization HACK from KVM RISC-V
before more supervisor software starts depending on it.

Regards,
Anup