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Tue, 13 May 2025 23:43:37 -0700 (PDT) From: Atish Patra Date: Tue, 13 May 2025 23:43:30 -0700 Subject: [PATCH] RISC-V: KVM: Disable instret/cycle for VU mode by default Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250513-fix_scounteren_vs-v1-1-c1f52af93c79@rivosinc.com> X-B4-Tracking: v=1; b=H4sIAJE7JGgC/x2MQQqAIBAAvxJ7TijDjL4SIaVr7cXCLQmkvycdB 2YmA2MkZBirDBETMR2hQFtXYPclbCjIFQbZSNWothOeHsP2uMOFEYNJLLxzQy+VsnrVULozYpH +5zS/7wdhSXygYwAAAA== X-Change-ID: 20250513-fix_scounteren_vs-fdd86255c7b7 To: Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Alexandre Ghiti Cc: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-42535 The KVM virtualizes PMU in RISC-V and disables all counter access except TM bit by default vi hstateen CSR. There is no benefit in enabling CY/TM bits in scounteren for the guest user space as it can't be run without hcounteren anyways. Allow only TM bit which matches the hcounteren default setting. Signed-off-by: Atish Patra --- arch/riscv/kvm/vcpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 60d684c76c58..873593bfe610 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -146,8 +146,8 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) if (kvm_riscv_vcpu_alloc_vector_context(vcpu, cntx)) return -ENOMEM; =20 - /* By default, make CY, TM, and IR counters accessible in VU mode */ - reset_csr->scounteren =3D 0x7; + /* By default, only TM should be accessible in VU mode */ + reset_csr->scounteren =3D 0x2; =20 /* Setup VCPU timer */ kvm_riscv_vcpu_timer_init(vcpu); --- base-commit: 01f95500a162fca88cefab9ed64ceded5afabc12 change-id: 20250513-fix_scounteren_vs-fdd86255c7b7 -- Regards, Atish patra