Add documentation and functionality for LLCC v6 used on
the SM8750 SoCs. LLCC v6 rearranges several registers and offsets
and supports slice IDs over 31, so new functionality is necessary
to program and use LLCC v6.
---
Changes in v5:
- Fixed indentation style on patch 2
- Fixed macro style on patch 2 (added parentesis to arguments)
- Link to v4: https://lore.kernel.org/r/20250414-sm8750_llcc_master-v4-0-e007f035380c@oss.qualcomm.com
Changes in v4:
- Updated cache data table for LLCC_WRCACHE to activate on init.
- Link to v3: https://lore.kernel.org/r/20250324-sm8750_llcc_master-v3-0-2afd5c0fdbde@quicinc.com
Changes in v3:
- Removed some unused variables.
- Added parent/child grouping features to v6
- Updated cache data table with up-to-date configurations
- Link to v2: https://lore.kernel.org/r/20250304-sm8750_llcc_master-v2-0-ae4e1949546e@quicinc.com
Changes in v2:
- moved v6 offsets into cfg struct
- reverse xmas-treed variable declarations & removed unused
- removed unneeded skip_llcc_cfg branch in v6
- updated some macros to use BITS, GENMASK, FIELD_PREP
- moved LLCC_* definitions to appropriate patch
- updated sm8750 slice data struct to match updated standard
- fixed style on dt node
- note: did not add cleanup patch to use bitfields
- Link to v1: https://lore.kernel.org/r/20250113-sm8750_llcc_master-v1-0-5389b92e2d7a@quicinc.com
---
Melody Olvera (4):
dt-bindings: cache: qcom,llcc: Document SM8750 LLCC block
soc: qcom: llcc-qcom: Add support for LLCC V6
soc: qcom: llcc-qcom: Add support for SM8750
arm64: dts: qcom: sm8750: Add LLCC node
.../devicetree/bindings/cache/qcom,llcc.yaml | 2 +
arch/arm64/boot/dts/qcom/sm8750.dtsi | 18 +
drivers/soc/qcom/llcc-qcom.c | 497 ++++++++++++++++++++-
include/linux/soc/qcom/llcc-qcom.h | 8 +
4 files changed, 521 insertions(+), 4 deletions(-)
---
base-commit: edef457004774e598fc4c1b7d1d4f0bcd9d0bb30
change-id: 20250107-sm8750_llcc_master-baa3de44b03b
Best regards,
--
Melody Olvera <melody.olvera@oss.qualcomm.com>