From: Frank Wunderlich <frank-w@public-files.de>
Add mt7988 builtin mt753x switch nodes.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 166 ++++++++++++++++++++++
1 file changed, 166 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
index aa0947a555aa..ab7612916a13 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -5,6 +5,7 @@
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/mt65xx.h>
#include <dt-bindings/reset/mediatek,mt7988-resets.h>
+#include <dt-bindings/leds/common.h>
/ {
compatible = "mediatek,mt7988a";
@@ -742,6 +743,171 @@ ethsys: clock-controller@15000000 {
#reset-cells = <1>;
};
+ switch: switch@15020000 {
+ compatible = "mediatek,mt7988-switch";
+ reg = <0 0x15020000 0 0x8000>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <ðwarp MT7988_ETHWARP_RST_SWITCH>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gsw_port0: port@0 {
+ reg = <0>;
+ label = "wan";
+ phy-mode = "internal";
+ phy-handle = <&gsw_phy0>;
+ };
+
+ gsw_port1: port@1 {
+ reg = <1>;
+ label = "lan1";
+ phy-mode = "internal";
+ phy-handle = <&gsw_phy1>;
+ };
+
+ gsw_port2: port@2 {
+ reg = <2>;
+ label = "lan2";
+ phy-mode = "internal";
+ phy-handle = <&gsw_phy2>;
+ };
+
+ gsw_port3: port@3 {
+ reg = <3>;
+ label = "lan3";
+ phy-mode = "internal";
+ phy-handle = <&gsw_phy3>;
+ };
+
+ port@6 {
+ reg = <6>;
+ ethernet = <&gmac0>;
+ phy-mode = "internal";
+
+ fixed-link {
+ speed = <10000>;
+ full-duplex;
+ pause;
+ };
+ };
+ };
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mediatek,pio = <&pio>;
+
+ gsw_phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ interrupts = <0>;
+ phy-mode = "internal";
+ nvmem-cells = <&phy_calibration_p0>;
+ nvmem-cell-names = "phy-cal-data";
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gsw_phy0_led0: led@0 {
+ reg = <0>;
+ function = LED_FUNCTION_LAN;
+ status = "disabled";
+ };
+
+ gsw_phy0_led1: led@1 {
+ reg = <1>;
+ function = LED_FUNCTION_LAN;
+ status = "disabled";
+ };
+ };
+ };
+
+ gsw_phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ interrupts = <1>;
+ phy-mode = "internal";
+ nvmem-cells = <&phy_calibration_p1>;
+ nvmem-cell-names = "phy-cal-data";
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gsw_phy1_led0: led@0 {
+ reg = <0>;
+ function = LED_FUNCTION_LAN;
+ status = "disabled";
+ };
+
+ gsw_phy1_led1: led@1 {
+ reg = <1>;
+ function = LED_FUNCTION_LAN;
+ status = "disabled";
+ };
+ };
+ };
+
+ gsw_phy2: ethernet-phy@2 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <2>;
+ interrupts = <2>;
+ phy-mode = "internal";
+ nvmem-cells = <&phy_calibration_p2>;
+ nvmem-cell-names = "phy-cal-data";
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gsw_phy2_led0: led@0 {
+ reg = <0>;
+ function = LED_FUNCTION_LAN;
+ status = "disabled";
+ };
+
+ gsw_phy2_led1: led@1 {
+ reg = <1>;
+ function = LED_FUNCTION_LAN;
+ status = "disabled";
+ };
+ };
+ };
+
+ gsw_phy3: ethernet-phy@3 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <3>;
+ interrupts = <3>;
+ phy-mode = "internal";
+ nvmem-cells = <&phy_calibration_p3>;
+ nvmem-cell-names = "phy-cal-data";
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gsw_phy3_led0: led@0 {
+ reg = <0>;
+ function = LED_FUNCTION_LAN;
+ status = "disabled";
+ };
+
+ gsw_phy3_led1: led@1 {
+ reg = <1>;
+ function = LED_FUNCTION_LAN;
+ status = "disabled";
+ };
+ };
+ };
+ };
+ };
+
ethwarp: clock-controller@15031000 {
compatible = "mediatek,mt7988-ethwarp";
reg = <0 0x15031000 0 0x1000>;
--
2.43.0
On Sun, May 11, 2025 at 04:19:25PM +0200, Frank Wunderlich wrote:
> From: Frank Wunderlich <frank-w@public-files.de>
>
> Add mt7988 builtin mt753x switch nodes.
>
> Signed-off-by: Daniel Golle <daniel@makrotopia.org>
> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
> ---
> arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 166 ++++++++++++++++++++++
> 1 file changed, 166 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
> index aa0947a555aa..ab7612916a13 100644
> --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
> @@ -5,6 +5,7 @@
> #include <dt-bindings/phy/phy.h>
> #include <dt-bindings/pinctrl/mt65xx.h>
> #include <dt-bindings/reset/mediatek,mt7988-resets.h>
> +#include <dt-bindings/leds/common.h>
>
> / {
> compatible = "mediatek,mt7988a";
> @@ -742,6 +743,171 @@ ethsys: clock-controller@15000000 {
> #reset-cells = <1>;
> };
>
> + switch: switch@15020000 {
> + compatible = "mediatek,mt7988-switch";
> + reg = <0 0x15020000 0 0x8000>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
> + resets = <ðwarp MT7988_ETHWARP_RST_SWITCH>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + gsw_port0: port@0 {
> + reg = <0>;
> + label = "wan";
I would expect the label to be in the board .dts file, since it is a
board property, not a SoC property.
Andrew
> Gesendet: Sonntag, 11. Mai 2025 um 18:42
> Von: "Andrew Lunn" <andrew@lunn.ch>
> Betreff: Re: [PATCH v1 09/14] arm64: dts: mediatek: mt7988: add switch node
>
> On Sun, May 11, 2025 at 04:19:25PM +0200, Frank Wunderlich wrote:
> > From: Frank Wunderlich <frank-w@public-files.de>
> >
> > Add mt7988 builtin mt753x switch nodes.
> >
> > Signed-off-by: Daniel Golle <daniel@makrotopia.org>
> > Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
> > ---
> > arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 166 ++++++++++++++++++++++
> > 1 file changed, 166 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
> > index aa0947a555aa..ab7612916a13 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
> > @@ -5,6 +5,7 @@
> > #include <dt-bindings/phy/phy.h>
> > #include <dt-bindings/pinctrl/mt65xx.h>
> > #include <dt-bindings/reset/mediatek,mt7988-resets.h>
> > +#include <dt-bindings/leds/common.h>
> >
> > / {
> > compatible = "mediatek,mt7988a";
> > @@ -742,6 +743,171 @@ ethsys: clock-controller@15000000 {
> > #reset-cells = <1>;
> > };
> >
> > + switch: switch@15020000 {
> > + compatible = "mediatek,mt7988-switch";
> > + reg = <0 0x15020000 0 0x8000>;
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + interrupt-parent = <&gic>;
> > + interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
> > + resets = <ðwarp MT7988_ETHWARP_RST_SWITCH>;
> > +
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + gsw_port0: port@0 {
> > + reg = <0>;
> > + label = "wan";
>
> I would expect the label to be in the board .dts file, since it is a
> board property, not a SoC property.
i will move that into the board dtsi file in v2 because "normal" bpi-r4 and 2g5 variant are same here.
regards Frank
> i will move that into the board dtsi file in v2 because "normal" bpi-r4 and 2g5 variant are same here. Maybe you just need to expand the commit message? What does this .dtsi actually represent? The SoC, or what is common across a number of boards? Andrew
On Sun, May 11, 2025 at 11:25:27PM +0200, Andrew Lunn wrote: > > i will move that into the board dtsi file in v2 because "normal" bpi-r4 and 2g5 variant are same here. > > Maybe you just need to expand the commit message? What does this .dtsi > actually represent? The SoC, or what is common across a number of > boards? mt7988a.dtsi represents the SoC, and thus there shouldn't be any labels assigned to the DSA ports. In case of the BananaPi R4 there are two different boards, one with 2x SFP+ and one with 1x SFP+ + 1x 2500Base-T (with PoE-in), hence there is a dtsi files for all the parts shared among the two boards. I suppose Frank meant to move the labels to that board dtsi file, and that's correct imho as the labels of the 1G switch ports are the same on BPi-R4 and BPi-R4-PoE.
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