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(fttx-pool-194.15.84.99.bambit.de [194.15.84.99]) by mxbox2.masterlogin.de (Postfix) with ESMTPSA id A5D6D100787; Sun, 11 May 2025 14:20:00 +0000 (UTC) From: Frank Wunderlich To: Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno Cc: Frank Wunderlich , =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Landen Chao , DENG Qingfang , Sean Wang , Daniel Golle , Lorenzo Bianconi , Felix Fietkau , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v1 09/14] arm64: dts: mediatek: mt7988: add switch node Date: Sun, 11 May 2025 16:19:25 +0200 Message-ID: <20250511141942.10284-10-linux@fw-web.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250511141942.10284-1-linux@fw-web.de> References: <20250511141942.10284-1-linux@fw-web.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Mail-ID: a24ecea1-b7fd-4cb4-a93d-b29036e2e6ac Content-Type: text/plain; charset="utf-8" From: Frank Wunderlich Add mt7988 builtin mt753x switch nodes. Signed-off-by: Daniel Golle Signed-off-by: Frank Wunderlich --- arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 166 ++++++++++++++++++++++ 1 file changed, 166 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dt= s/mediatek/mt7988a.dtsi index aa0947a555aa..ab7612916a13 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -5,6 +5,7 @@ #include #include #include +#include =20 / { compatible =3D "mediatek,mt7988a"; @@ -742,6 +743,171 @@ ethsys: clock-controller@15000000 { #reset-cells =3D <1>; }; =20 + switch: switch@15020000 { + compatible =3D "mediatek,mt7988-switch"; + reg =3D <0 0x15020000 0 0x8000>; + interrupt-controller; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + resets =3D <ðwarp MT7988_ETHWARP_RST_SWITCH>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + gsw_port0: port@0 { + reg =3D <0>; + label =3D "wan"; + phy-mode =3D "internal"; + phy-handle =3D <&gsw_phy0>; + }; + + gsw_port1: port@1 { + reg =3D <1>; + label =3D "lan1"; + phy-mode =3D "internal"; + phy-handle =3D <&gsw_phy1>; + }; + + gsw_port2: port@2 { + reg =3D <2>; + label =3D "lan2"; + phy-mode =3D "internal"; + phy-handle =3D <&gsw_phy2>; + }; + + gsw_port3: port@3 { + reg =3D <3>; + label =3D "lan3"; + phy-mode =3D "internal"; + phy-handle =3D <&gsw_phy3>; + }; + + port@6 { + reg =3D <6>; + ethernet =3D <&gmac0>; + phy-mode =3D "internal"; + + fixed-link { + speed =3D <10000>; + full-duplex; + pause; + }; + }; + }; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + mediatek,pio =3D <&pio>; + + gsw_phy0: ethernet-phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0>; + interrupts =3D <0>; + phy-mode =3D "internal"; + nvmem-cells =3D <&phy_calibration_p0>; + nvmem-cell-names =3D "phy-cal-data"; + + leds { + #address-cells =3D <1>; + #size-cells =3D <0>; + + gsw_phy0_led0: led@0 { + reg =3D <0>; + function =3D LED_FUNCTION_LAN; + status =3D "disabled"; + }; + + gsw_phy0_led1: led@1 { + reg =3D <1>; + function =3D LED_FUNCTION_LAN; + status =3D "disabled"; + }; + }; + }; + + gsw_phy1: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + interrupts =3D <1>; + phy-mode =3D "internal"; + nvmem-cells =3D <&phy_calibration_p1>; + nvmem-cell-names =3D "phy-cal-data"; + + leds { + #address-cells =3D <1>; + #size-cells =3D <0>; + + gsw_phy1_led0: led@0 { + reg =3D <0>; + function =3D LED_FUNCTION_LAN; + status =3D "disabled"; + }; + + gsw_phy1_led1: led@1 { + reg =3D <1>; + function =3D LED_FUNCTION_LAN; + status =3D "disabled"; + }; + }; + }; + + gsw_phy2: ethernet-phy@2 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <2>; + interrupts =3D <2>; + phy-mode =3D "internal"; + nvmem-cells =3D <&phy_calibration_p2>; + nvmem-cell-names =3D "phy-cal-data"; + + leds { + #address-cells =3D <1>; + #size-cells =3D <0>; + + gsw_phy2_led0: led@0 { + reg =3D <0>; + function =3D LED_FUNCTION_LAN; + status =3D "disabled"; + }; + + gsw_phy2_led1: led@1 { + reg =3D <1>; + function =3D LED_FUNCTION_LAN; + status =3D "disabled"; + }; + }; + }; + + gsw_phy3: ethernet-phy@3 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <3>; + interrupts =3D <3>; + phy-mode =3D "internal"; + nvmem-cells =3D <&phy_calibration_p3>; + nvmem-cell-names =3D "phy-cal-data"; + + leds { + #address-cells =3D <1>; + #size-cells =3D <0>; + + gsw_phy3_led0: led@0 { + reg =3D <0>; + function =3D LED_FUNCTION_LAN; + status =3D "disabled"; + }; + + gsw_phy3_led1: led@1 { + reg =3D <1>; + function =3D LED_FUNCTION_LAN; + status =3D "disabled"; + }; + }; + }; + }; + }; + ethwarp: clock-controller@15031000 { compatible =3D "mediatek,mt7988-ethwarp"; reg =3D <0 0x15031000 0 0x1000>; --=20 2.43.0