This adds support for DSS subsystem present in TI's AM62L SoC
which supports single display pipeline with DPI output which
is also routed to DSI Tx controller within the SoC.

Change Log:
V6: 
- Move hw_id indexing logic to skip uninstantiated planes to
  internal functions dealing with relevant registers

V5:
- Use hw_id instead of index for places where it was missed
  so that we pick correct base address for vid region

V4:
- Update vid_info struct to keep hw_id and instantiate
  only for actually existing pipes

V3:
- Make generic infra to support truncated K3 DSS IP's
- Remove AM62A updates from AM62L DT binding updates

V2:
- Fix incorrect format of compatible string (comma instead of
  hyphen) for AM62L SoC
- Use separate register space and helper functions for AM62L
  due to minor differences in register offset/bit position differences
  for first plane

Rangediff:
V5->V6:
- https://gist.github.com/devarsht/f64b00754794d22e57ac18ec09a7b019

V4->V5:
- https://gist.github.com/devarsht/a0e6aa7b1c19f47facd0058962e3c3c2

V3->V4:
- https://gist.github.com/devarsht/1e75c9e1ac0cdfc01703a0776e31e782

V2->V3:
- https://gist.github.com/devarsht/24fa8dd2986861efa431352d19ebbb41

V1->V2
- https://gist.github.com/devarsht/11d47f25ca9fea6976e6284330ddf443

Links to previous versions:
V5: https://lore.kernel.org/all/20250429143656.3252877-1-devarsht@ti.com/
V4: https://lore.kernel.org/all/20250326145736.3659670-1-devarsht@ti.com/
V3: https://lore.kernel.org/all/20250306132914.1469387-1-devarsht@ti.com/
V2: https://lore.kernel.org/all/20250204061552.3720261-1-devarsht@ti.com/
V1: https://lore.kernel.org/all/20241231090432.3649158-1-devarsht@ti.com/

Test logs:
https://gist.github.com/devarsht/09a5d64a507b7ccc096e857f122eda70

Devarsh Thakkar (3):
  dt-bindings: display: ti,am65x-dss: Add support for AM62L DSS
  drm/tidss: Update infrastructure to support K3 DSS cut-down versions
  drm/tidss: Add support for AM62L display subsystem

 .../bindings/display/ti/ti,am65x-dss.yaml     |  21 +-
 drivers/gpu/drm/tidss/tidss_crtc.c            |   4 +-
 drivers/gpu/drm/tidss/tidss_dispc.c           | 197 ++++++++++++++----
 drivers/gpu/drm/tidss/tidss_dispc.h           |  13 +-
 drivers/gpu/drm/tidss/tidss_drv.c             |   1 +
 drivers/gpu/drm/tidss/tidss_kms.c             |   2 +-
 drivers/gpu/drm/tidss/tidss_plane.c           |   2 +-
 7 files changed, 192 insertions(+), 48 deletions(-)

-- 
2.39.1

Hi,

On 07/05/2025 21:06, Devarsh Thakkar wrote:
> This adds support for DSS subsystem present in TI's AM62L SoC
> which supports single display pipeline with DPI output which
> is also routed to DSI Tx controller within the SoC.

I think this looks fine. I did some quick tests, and didn't notice 
anything amiss. I'm still somewhat wary about the indexing we do wrt. 
planes, and the possibility to introduce hard-to-find bugs by using the 
wrong index. We can try to improve this on top.

Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>

I'll do a few more tests, and unless there are no other commets I'll 
push to drm-misc tomorrow.

  Tomi