From nobody Sun Dec 14 06:20:52 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D11EE2571D7; Wed, 7 May 2025 18:07:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746641223; cv=none; b=lojsQuVVDgvga0Xm5wZKz0kOf4SRYhZ7ww79GPc5E3CbS6TsxRzuWCpXkz+bAfIYYLoE6sqhlqdCUzI3sTmMHsIaxr92ZOuGg938yB3qp3qftpSEYLvLiqCKuLZzasJsVu70ZohX8Wy0ihjI8bXy6NfgmJ0FiDUghhcFnpEejV4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746641223; c=relaxed/simple; bh=UvpazV8xQU9HRRLul36TI7uDwHlchqfCivv8W6F7Pp8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=V4xsk4yuRLdQoL/kMPl7X6IcyA+CaZIqytuK5h0u1zoB4gHOnoJpqTkSnaeJbhHsaGmT1oRksWjBvvmgfa/F2Db6pfhEOLun9KleVNlfOxtiwf1CUjxL1tc84dM9lKoZYfgtrapuKLEC225wSnQZiIdUpjbTbb+aPQzVV58dHSE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=L3CNQJ3y; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="L3CNQJ3y" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 547I6ZZR1594640 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 7 May 2025 13:06:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1746641195; bh=0+UCHzmZyl1chqLqX2QUWcfk6t5klutwQR47DtTuYJM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=L3CNQJ3y927oYg9doFlxj/w4vMt39TQj07e8CQqdpjfSGUd+tu14j4I81HF1XqwkJ LQVFPfPmq1uYqUO3mMPueWW8wKSAT8QXGtggSWM+nzhnMp+UyNM9JSg8eEQqcE7Z+c kD9IPNWVkJe7dhgJ6bd3pbgXZ7d32evcBEk8LP70= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 547I6Zb1012470 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 7 May 2025 13:06:35 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 7 May 2025 13:06:34 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 7 May 2025 13:06:34 -0500 Received: from localhost (ti.dhcp.ti.com [172.24.227.95] (may be forged)) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 547I6XJA086337; Wed, 7 May 2025 13:06:34 -0500 From: Devarsh Thakkar To: , , , , , , , , , , , , CC: , , , , , , , Subject: [PATCH v6 1/3] dt-bindings: display: ti,am65x-dss: Add support for AM62L DSS Date: Wed, 7 May 2025 23:36:29 +0530 Message-ID: <20250507180631.874930-2-devarsht@ti.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20250507180631.874930-1-devarsht@ti.com> References: <20250507180631.874930-1-devarsht@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The DSS controller on TI's AM62L SoC is an update from that on TI's AM625/AM65x/AM62A7 SoC. The AM62L DSS [1] only supports a single display pipeline using a single overlay manager, single video port and a single video lite pipeline which does not support scaling. The output of video port is routed to SoC boundary via DPI interface and the DPI signals from the video port are also routed to DSI Tx controller present within the SoC. [1]: Section 11.7 (Display Subsystem and Peripherals) Link : https://www.ti.com/lit/pdf/sprujb4 Reviewed-by: Krzysztof Kozlowski Reviewed-by: Jayesh Choudhary Reviewed-by: Tomi Valkeinen Signed-off-by: Devarsh Thakkar --- V6: No change V5: No change V4: No change V3: - Remove AM62A references as suggested - Add Reviewed-by V2:=20 - Add Reviewed-by - s/ti,am62l,dss/ti,am62l-dss .../bindings/display/ti/ti,am65x-dss.yaml | 21 ++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml= b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml index 31c4ffcb599c..a5b13cb7bc73 100644 --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml @@ -12,18 +12,25 @@ maintainers: - Tomi Valkeinen =20 description: | - The AM625 and AM65x TI Keystone Display SubSystem with two output + The AM625 and AM65x TI Keystone Display SubSystem has two output ports and two video planes. In AM65x DSS, the first video port supports 1 OLDI TX and in AM625 DSS, the first video port output is internally routed to 2 OLDI TXes. The second video port supports DPI format. The first plane is full video plane with all features and the second is a "lite plane" without scaling support. + The AM62L display subsystem has a single output port which supports DPI + format but it only supports single video "lite plane" which does not sup= port + scaling. The output port is routed to SoC boundary via DPI interface and= same + DPI signals are also routed internally to DSI Tx controller present with= in the + SoC. Due to clocking limitations only one of the interface i.e. either D= SI or + DPI can be used at once. =20 properties: compatible: enum: - ti,am625-dss - ti,am62a7-dss + - ti,am62l-dss - ti,am65x-dss =20 reg: @@ -91,6 +98,8 @@ properties: For AM625 DSS, the internal DPI output port node from video port 1. For AM62A7 DSS, the port is tied off inside the SoC. + For AM62L DSS, the DSS DPI output port node from video port 1 + or DSI Tx controller node connected to video port 1. =20 port@1: $ref: /schemas/graph.yaml#/properties/port @@ -123,6 +132,16 @@ allOf: ports: properties: port@0: false + - if: + properties: + compatible: + contains: + const: ti,am62l-dss + then: + properties: + ports: + properties: + port@1: false =20 required: - compatible --=20 2.39.1 From nobody Sun Dec 14 06:20:52 2025 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3EC2228DF29; Wed, 7 May 2025 18:07:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746641248; cv=none; b=MRaL2rTdYYOCn1qP9xo9rr690qlKeFeuSPV1lvhez5JIDeMY0tzxH+ceBODW7R2JtYuKU3voyBeNbSlK4yJglVIjBGWhsmAQNWSA8/Qq9xVReC6wVJx08otYf7xEX/22xB2NZYLjuzFZYcPeybbqg7ZvNo6Cqb1FcsTkvSFvZ0Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746641248; c=relaxed/simple; bh=1fuS32mnyjY83FDqXDt52ebdxPy9J4jG3x+QCtGNGYA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ZC22UfHmyPEUAQm6Po7wqAeX9Ew1/rodJ0d/2Hi57bMA8ndbN62rAbgxp6sRBCYMjzDZtk3+UHIDJG2pEM2y0LPBAl53uE6YDAJ0Dv/kOI/hA8FLYKbPtUico0i7NDYjXIE2LsijXa3UrKeOD4eclOS6VpmwztjOvK9+jHzWwEU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=UsvynC7s; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="UsvynC7s" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 547I6a1o880336 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 7 May 2025 13:06:37 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1746641197; bh=SsqShv+r+IYKB1CxAQfhmkupLRrQkbI42y1oFy7KwTk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=UsvynC7s6mI7NtLEcbLcri2NewGzoXBL428w3MWnVe1oVTTR5isWFuowHxf+ouR97 7wZp4Ewwhx8x5pmdl/VfOcdUXy0HXugZwSt7uXBfAU8rKx9FZRv1HTpla08XNoCSFI JQifdytnMpTOMfSWjWxiIgsBrtlnFQ96CkquDE+E= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 547I6art035030 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 7 May 2025 13:06:36 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 7 May 2025 13:06:36 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 7 May 2025 13:06:36 -0500 Received: from localhost (ti.dhcp.ti.com [172.24.227.95] (may be forged)) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 547I6ZDZ086354; Wed, 7 May 2025 13:06:35 -0500 From: Devarsh Thakkar To: , , , , , , , , , , , , CC: , , , , , , , Subject: [PATCH v6 2/3] drm/tidss: Update infrastructure to support K3 DSS cut-down versions Date: Wed, 7 May 2025 23:36:30 +0530 Message-ID: <20250507180631.874930-3-devarsht@ti.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20250507180631.874930-1-devarsht@ti.com> References: <20250507180631.874930-1-devarsht@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" SoCs like AM62Lx support cut-down version of K3 DSS where although same register space is supported as in other K3 DSS supported SoCs such as AM65x, AM62x, AM62Ax but some of the resources such as planes and corresponding register spaces are truncated. For e.g. AM62Lx has only single VIDL pipeline supported, so corresponding register spaces for other video pipelines need to be skipped. To add a generic support for future SoCs where one or more video pipelines can get truncated from the parent register space, move the video plane related information to vid_info struct which will also have a field to indicate hardware index of each of the available video planes, so that driver only maps and programs those video pipes and skips the unavailable ones. While at it, also change the num_planes field in the features structure to num_vid so that all places in code which use vid_info structure are highlighted in the code. Signed-off-by: Devarsh Thakkar Reviewed-by: Tomi Valkeinen --- V6: - Move hw_id indexing logic to skip uninstantiated planes to internal functions dealing with relevant registers V5: - Use separate variable for hw_id and add it in missing places to access correct VID pipeline bits in common registers V4: - Create vid_info struct only for instantiated planes - s/num_planes/num_vids - s/vid_lite/is_lite - Add hw_id member in vid_info struct and remove is_present V2->V3: - No change (patch introduced in V3) drivers/gpu/drm/tidss/tidss_crtc.c | 4 +- drivers/gpu/drm/tidss/tidss_dispc.c | 154 +++++++++++++++++++++------- drivers/gpu/drm/tidss/tidss_dispc.h | 11 +- drivers/gpu/drm/tidss/tidss_kms.c | 2 +- drivers/gpu/drm/tidss/tidss_plane.c | 2 +- 5 files changed, 127 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_crtc.c b/drivers/gpu/drm/tidss/tid= ss_crtc.c index 94f8e3178df5..a2f40a5c7703 100644 --- a/drivers/gpu/drm/tidss/tidss_crtc.c +++ b/drivers/gpu/drm/tidss/tidss_crtc.c @@ -130,7 +130,7 @@ static void tidss_crtc_position_planes(struct tidss_dev= ice *tidss, !to_tidss_crtc_state(cstate)->plane_pos_changed) return; =20 - for (layer =3D 0; layer < tidss->feat->num_planes; layer++) { + for (layer =3D 0; layer < tidss->feat->num_vids ; layer++) { struct drm_plane_state *pstate; struct drm_plane *plane; bool layer_active =3D false; @@ -271,7 +271,7 @@ static void tidss_crtc_atomic_disable(struct drm_crtc *= crtc, * another videoport, the DSS will report sync lost issues. Disable all * the layers here as a work-around. */ - for (u32 layer =3D 0; layer < tidss->feat->num_planes; layer++) + for (u32 layer =3D 0; layer < tidss->feat->num_vids; layer++) dispc_ovr_enable_layer(tidss->dispc, tcrtc->hw_videoport, layer, false); =20 diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index cacb5f3d8085..774c608c88b5 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -103,9 +103,16 @@ const struct dispc_features dispc_k2g_feats =3D { }, }, =20 - .num_planes =3D 1, - .vid_name =3D { "vid1" }, - .vid_lite =3D { false }, + .num_vids =3D 1, + + .vid_info =3D { + { + .name =3D "vid1", + .is_lite =3D false, + .hw_id =3D 0, + }, + }, + .vid_order =3D { 0 }, }; =20 @@ -178,11 +185,22 @@ const struct dispc_features dispc_am65x_feats =3D { }, }, =20 - .num_planes =3D 2, + .num_vids =3D 2, /* note: vid is plane_id 0 and vidl1 is plane_id 1 */ - .vid_name =3D { "vid", "vidl1" }, - .vid_lite =3D { false, true, }, - .vid_order =3D { 1, 0 }, + .vid_info =3D { + { + .name =3D "vid", + .is_lite =3D false, + .hw_id =3D 0, + }, + { + .name =3D "vidl1", + .is_lite =3D true, + .hw_id =3D 1, + }, + }, + + .vid_order =3D {1, 0}, }; =20 static const u16 tidss_j721e_common_regs[DISPC_COMMON_REG_TABLE_LEN] =3D { @@ -267,9 +285,32 @@ const struct dispc_features dispc_j721e_feats =3D { .gamma_type =3D TIDSS_GAMMA_10BIT, }, }, - .num_planes =3D 4, - .vid_name =3D { "vid1", "vidl1", "vid2", "vidl2" }, - .vid_lite =3D { 0, 1, 0, 1, }, + + .num_vids =3D 4, + + .vid_info =3D { + { + .name =3D "vid1", + .is_lite =3D false, + .hw_id =3D 0, + }, + { + .name =3D "vidl1", + .is_lite =3D true, + .hw_id =3D 1, + }, + { + .name =3D "vid2", + .is_lite =3D false, + .hw_id =3D 2, + }, + { + .name =3D "vidl2", + .is_lite =3D true, + .hw_id =3D 3, + }, + }, + .vid_order =3D { 1, 3, 0, 2 }, }; =20 @@ -315,11 +356,23 @@ const struct dispc_features dispc_am625_feats =3D { }, }, =20 - .num_planes =3D 2, + .num_vids =3D 2, + /* note: vid is plane_id 0 and vidl1 is plane_id 1 */ - .vid_name =3D { "vid", "vidl1" }, - .vid_lite =3D { false, true, }, - .vid_order =3D { 1, 0 }, + .vid_info =3D { + { + .name =3D "vid", + .is_lite =3D false, + .hw_id =3D 0, + }, + { + .name =3D "vidl1", + .is_lite =3D true, + .hw_id =3D 1, + } + }, + + .vid_order =3D {1, 0}, }; =20 const struct dispc_features dispc_am62a7_feats =3D { @@ -369,11 +422,22 @@ const struct dispc_features dispc_am62a7_feats =3D { }, }, =20 - .num_planes =3D 2, - /* note: vid is plane_id 0 and vidl1 is plane_id 1 */ - .vid_name =3D { "vid", "vidl1" }, - .vid_lite =3D { false, true, }, - .vid_order =3D { 1, 0 }, + .num_vids =3D 2, + + .vid_info =3D { + { + .name =3D "vid", + .is_lite =3D false, + .hw_id =3D 0, + }, + { + .name =3D "vidl1", + .is_lite =3D true, + .hw_id =3D 1, + } + }, + + .vid_order =3D {1, 0}, }; =20 static const u16 *dispc_common_regmap; @@ -734,7 +798,8 @@ static void dispc_k3_vp_write_irqstatus(struct dispc_de= vice *dispc, static dispc_irq_t dispc_k3_vid_read_irqstatus(struct dispc_device *dispc, u32 hw_plane) { - u32 stat =3D dispc_read(dispc, DISPC_VID_IRQSTATUS(hw_plane)); + u32 hw_id =3D dispc->feat->vid_info[hw_plane].hw_id; + u32 stat =3D dispc_read(dispc, DISPC_VID_IRQSTATUS(hw_id)); =20 return dispc_vid_irq_from_raw(stat, hw_plane); } @@ -742,9 +807,10 @@ static dispc_irq_t dispc_k3_vid_read_irqstatus(struct = dispc_device *dispc, static void dispc_k3_vid_write_irqstatus(struct dispc_device *dispc, u32 hw_plane, dispc_irq_t vidstat) { + u32 hw_id =3D dispc->feat->vid_info[hw_plane].hw_id; u32 stat =3D dispc_vid_irq_to_raw(vidstat, hw_plane); =20 - dispc_write(dispc, DISPC_VID_IRQSTATUS(hw_plane), stat); + dispc_write(dispc, DISPC_VID_IRQSTATUS(hw_id), stat); } =20 static dispc_irq_t dispc_k3_vp_read_irqenable(struct dispc_device *dispc, @@ -766,7 +832,8 @@ static void dispc_k3_vp_set_irqenable(struct dispc_devi= ce *dispc, static dispc_irq_t dispc_k3_vid_read_irqenable(struct dispc_device *dispc, u32 hw_plane) { - u32 stat =3D dispc_read(dispc, DISPC_VID_IRQENABLE(hw_plane)); + u32 hw_id =3D dispc->feat->vid_info[hw_plane].hw_id; + u32 stat =3D dispc_read(dispc, DISPC_VID_IRQENABLE(hw_id)); =20 return dispc_vid_irq_from_raw(stat, hw_plane); } @@ -774,9 +841,10 @@ static dispc_irq_t dispc_k3_vid_read_irqenable(struct = dispc_device *dispc, static void dispc_k3_vid_set_irqenable(struct dispc_device *dispc, u32 hw_plane, dispc_irq_t vidstat) { + u32 hw_id =3D dispc->feat->vid_info[hw_plane].hw_id; u32 stat =3D dispc_vid_irq_to_raw(vidstat, hw_plane); =20 - dispc_write(dispc, DISPC_VID_IRQENABLE(hw_plane), stat); + dispc_write(dispc, DISPC_VID_IRQENABLE(hw_id), stat); } =20 static @@ -788,7 +856,8 @@ void dispc_k3_clear_irqstatus(struct dispc_device *disp= c, dispc_irq_t clearmask) if (clearmask & DSS_IRQ_VP_MASK(i)) dispc_k3_vp_write_irqstatus(dispc, i, clearmask); } - for (i =3D 0; i < dispc->feat->num_planes; ++i) { + + for (i =3D 0; i < dispc->feat->num_vids; ++i) { if (clearmask & DSS_IRQ_PLANE_MASK(i)) dispc_k3_vid_write_irqstatus(dispc, i, clearmask); } @@ -809,7 +878,7 @@ dispc_irq_t dispc_k3_read_and_clear_irqstatus(struct di= spc_device *dispc) for (i =3D 0; i < dispc->feat->num_vps; ++i) status |=3D dispc_k3_vp_read_irqstatus(dispc, i); =20 - for (i =3D 0; i < dispc->feat->num_planes; ++i) + for (i =3D 0; i < dispc->feat->num_vids; ++i) status |=3D dispc_k3_vid_read_irqstatus(dispc, i); =20 dispc_k3_clear_irqstatus(dispc, status); @@ -825,7 +894,7 @@ static dispc_irq_t dispc_k3_read_irqenable(struct dispc= _device *dispc) for (i =3D 0; i < dispc->feat->num_vps; ++i) enable |=3D dispc_k3_vp_read_irqenable(dispc, i); =20 - for (i =3D 0; i < dispc->feat->num_planes; ++i) + for (i =3D 0; i < dispc->feat->num_vids; ++i) enable |=3D dispc_k3_vid_read_irqenable(dispc, i); =20 return enable; @@ -851,12 +920,15 @@ static void dispc_k3_set_irqenable(struct dispc_devic= e *dispc, main_disable |=3D BIT(i); /* VP IRQ */ } =20 - for (i =3D 0; i < dispc->feat->num_planes; ++i) { + for (i =3D 0; i < dispc->feat->num_vids; ++i) { + u32 hw_id =3D dispc->feat->vid_info[i].hw_id; + dispc_k3_vid_set_irqenable(dispc, i, mask); + if (mask & DSS_IRQ_PLANE_MASK(i)) - main_enable |=3D BIT(i + 4); /* VID IRQ */ + main_enable |=3D BIT(hw_id + 4); /* VID IRQ */ else - main_disable |=3D BIT(i + 4); /* VID IRQ */ + main_disable |=3D BIT(hw_id + 4); /* VID IRQ */ } =20 if (main_enable) @@ -1358,8 +1430,10 @@ static void dispc_am65x_ovr_set_plane(struct dispc_d= evice *dispc, u32 hw_plane, u32 hw_videoport, u32 x, u32 y, u32 layer) { + u32 hw_id =3D dispc->feat->vid_info[hw_plane].hw_id; + OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), - hw_plane, 4, 1); + hw_id, 4, 1); OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), x, 17, 6); OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), @@ -1370,8 +1444,10 @@ static void dispc_j721e_ovr_set_plane(struct dispc_d= evice *dispc, u32 hw_plane, u32 hw_videoport, u32 x, u32 y, u32 layer) { + u32 hw_id =3D dispc->feat->vid_info[hw_plane].hw_id; + OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), - hw_plane, 4, 1); + hw_id, 4, 1); OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer), x, 13, 0); OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer), @@ -2025,7 +2101,7 @@ int dispc_plane_check(struct dispc_device *dispc, u32= hw_plane, const struct drm_plane_state *state, u32 hw_videoport) { - bool lite =3D dispc->feat->vid_lite[hw_plane]; + bool lite =3D dispc->feat->vid_info[hw_plane].is_lite; u32 fourcc =3D state->fb->format->format; bool need_scaling =3D state->src_w >> 16 !=3D state->crtc_w || state->src_h >> 16 !=3D state->crtc_h; @@ -2096,7 +2172,7 @@ void dispc_plane_setup(struct dispc_device *dispc, u3= 2 hw_plane, const struct drm_plane_state *state, u32 hw_videoport) { - bool lite =3D dispc->feat->vid_lite[hw_plane]; + bool lite =3D dispc->feat->vid_info[hw_plane].is_lite; u32 fourcc =3D state->fb->format->format; u16 cpp =3D state->fb->format->cpp[0]; u32 fb_width =3D state->fb->pitches[0] / cpp; @@ -2210,7 +2286,7 @@ static void dispc_k2g_plane_init(struct dispc_device = *dispc) /* MFLAG_START =3D MFLAGNORMALSTARTMODE */ REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6); =20 - for (hw_plane =3D 0; hw_plane < dispc->feat->num_planes; hw_plane++) { + for (hw_plane =3D 0; hw_plane < dispc->feat->num_vids; hw_plane++) { u32 size =3D dispc_vid_get_fifo_size(dispc, hw_plane); u32 thr_low, thr_high; u32 mflag_low, mflag_high; @@ -2226,7 +2302,7 @@ static void dispc_k2g_plane_init(struct dispc_device = *dispc) =20 dev_dbg(dispc->dev, "%s: bufsize %u, buf_threshold %u/%u, mflag threshold %u/%u preload %u\= n", - dispc->feat->vid_name[hw_plane], + dispc->feat->vid_info[hw_plane].name, size, thr_high, thr_low, mflag_high, mflag_low, @@ -2265,7 +2341,7 @@ static void dispc_k3_plane_init(struct dispc_device *= dispc) /* MFLAG_START =3D MFLAGNORMALSTARTMODE */ REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6); =20 - for (hw_plane =3D 0; hw_plane < dispc->feat->num_planes; hw_plane++) { + for (hw_plane =3D 0; hw_plane < dispc->feat->num_vids; hw_plane++) { u32 size =3D dispc_vid_get_fifo_size(dispc, hw_plane); u32 thr_low, thr_high; u32 mflag_low, mflag_high; @@ -2281,7 +2357,7 @@ static void dispc_k3_plane_init(struct dispc_device *= dispc) =20 dev_dbg(dispc->dev, "%s: bufsize %u, buf_threshold %u/%u, mflag threshold %u/%u preload %u\= n", - dispc->feat->vid_name[hw_plane], + dispc->feat->vid_info[hw_plane].name, size, thr_high, thr_low, mflag_high, mflag_low, @@ -2898,8 +2974,8 @@ int dispc_init(struct tidss_device *tidss) if (r) return r; =20 - for (i =3D 0; i < dispc->feat->num_planes; i++) { - r =3D dispc_iomap_resource(pdev, dispc->feat->vid_name[i], + for (i =3D 0; i < dispc->feat->num_vids; i++) { + r =3D dispc_iomap_resource(pdev, dispc->feat->vid_info[i].name, &dispc->base_vid[i]); if (r) return r; diff --git a/drivers/gpu/drm/tidss/tidss_dispc.h b/drivers/gpu/drm/tidss/ti= dss_dispc.h index 086327d51a90..72a0146e57d5 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.h +++ b/drivers/gpu/drm/tidss/tidss_dispc.h @@ -46,6 +46,12 @@ struct dispc_features_scaling { u32 xinc_max; }; =20 +struct dispc_vid_info { + const char *name; /* Should match dt reg names */ + u32 hw_id; + bool is_lite; +}; + struct dispc_errata { bool i2000; /* DSS Does Not Support YUV Pixel Data Formats */ }; @@ -82,9 +88,8 @@ struct dispc_features { const char *vpclk_name[TIDSS_MAX_PORTS]; /* Should match dt clk names */ const enum dispc_vp_bus_type vp_bus_type[TIDSS_MAX_PORTS]; struct tidss_vp_feat vp_feat; - u32 num_planes; - const char *vid_name[TIDSS_MAX_PLANES]; /* Should match dt reg names */ - bool vid_lite[TIDSS_MAX_PLANES]; + u32 num_vids; + struct dispc_vid_info vid_info[TIDSS_MAX_PLANES]; u32 vid_order[TIDSS_MAX_PLANES]; }; =20 diff --git a/drivers/gpu/drm/tidss/tidss_kms.c b/drivers/gpu/drm/tidss/tids= s_kms.c index f371518f8697..19432c08ec6b 100644 --- a/drivers/gpu/drm/tidss/tidss_kms.c +++ b/drivers/gpu/drm/tidss/tidss_kms.c @@ -115,7 +115,7 @@ static int tidss_dispc_modeset_init(struct tidss_device= *tidss) =20 const struct dispc_features *feat =3D tidss->feat; u32 max_vps =3D feat->num_vps; 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Wed, 7 May 2025 13:06:38 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 7 May 2025 13:06:37 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 7 May 2025 13:06:37 -0500 Received: from localhost (ti.dhcp.ti.com [172.24.227.95] (may be forged)) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 547I6aUo035982; Wed, 7 May 2025 13:06:37 -0500 From: Devarsh Thakkar To: , , , , , , , , , , , , CC: , , , , , , , Subject: [PATCH v6 3/3] drm/tidss: Add support for AM62L display subsystem Date: Wed, 7 May 2025 23:36:31 +0530 Message-ID: <20250507180631.874930-4-devarsht@ti.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20250507180631.874930-1-devarsht@ti.com> References: <20250507180631.874930-1-devarsht@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Enable display for AM62L DSS [1] which supports only a single display pipeline using a single overlay manager, single video port and a single video lite pipeline which does not support scaling. The output of video port is routed to SoC boundary via DPI interface and the DPI signals from the video port are also routed to DSI Tx controller present within the SoC. [1]: Section 11.7 (Display Subsystem and Peripherals) Link : https://www.ti.com/lit/pdf/sprujb4 Signed-off-by: Devarsh Thakkar Reviewed-by: Tomi Valkeinen --- v6: - No change V5: - No change V4: - Rebase on top of previous patch to use vid_info structure V3:=20 - Rebase on top of 0002-drm-tidss-Update-infra-to-support-DSS7-cut-down-vers.patch - Use the generic "tidss_am65x_common_regs" as common reg space instead of creating a new one V2:=20 - Add separate common reg space for AM62L - Add separate irq enable/disable/read/clear helpers for AM62L - Use separate helper function for setting overlay attributes - Drop Reviewed-by: Tomi Valkeinen due to additional changes made in V2. drivers/gpu/drm/tidss/tidss_dispc.c | 41 +++++++++++++++++++++++++++++ drivers/gpu/drm/tidss/tidss_dispc.h | 2 ++ drivers/gpu/drm/tidss/tidss_drv.c | 1 + 3 files changed, 44 insertions(+) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index f8bd005709d4..eb02c89705b3 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -440,6 +440,42 @@ const struct dispc_features dispc_am62a7_feats =3D { .vid_order =3D {1, 0}, }; =20 +const struct dispc_features dispc_am62l_feats =3D { + .max_pclk_khz =3D { + [DISPC_VP_DPI] =3D 165000, + }, + + .subrev =3D DISPC_AM62L, + + .common =3D "common", + .common_regs =3D tidss_am65x_common_regs, + + .num_vps =3D 1, + .vp_name =3D { "vp1" }, + .ovr_name =3D { "ovr1" }, + .vpclk_name =3D { "vp1" }, + .vp_bus_type =3D { DISPC_VP_DPI }, + + .vp_feat =3D { .color =3D { + .has_ctm =3D true, + .gamma_size =3D 256, + .gamma_type =3D TIDSS_GAMMA_8BIT, + }, + }, + + .num_vids =3D 1, + + .vid_info =3D { + { + .name =3D "vidl1", + .is_lite =3D true, + .hw_id =3D 1, + } + }, + + .vid_order =3D {0}, +}; + static const u16 *dispc_common_regmap; =20 struct dss_vp_data { @@ -951,6 +987,7 @@ dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc= _device *dispc) return dispc_k2g_read_and_clear_irqstatus(dispc); case DISPC_AM625: case DISPC_AM62A7: + case DISPC_AM62L: case DISPC_AM65X: case DISPC_J721E: return dispc_k3_read_and_clear_irqstatus(dispc); @@ -968,6 +1005,7 @@ void dispc_set_irqenable(struct dispc_device *dispc, d= ispc_irq_t mask) break; case DISPC_AM625: case DISPC_AM62A7: + case DISPC_AM62L: case DISPC_AM65X: case DISPC_J721E: dispc_k3_set_irqenable(dispc, mask); @@ -1464,6 +1502,7 @@ void dispc_ovr_set_plane(struct dispc_device *dispc, = u32 hw_plane, break; case DISPC_AM625: case DISPC_AM62A7: + case DISPC_AM62L: case DISPC_AM65X: dispc_am65x_ovr_set_plane(dispc, hw_plane, hw_videoport, x, y, layer); @@ -2384,6 +2423,7 @@ static void dispc_plane_init(struct dispc_device *dis= pc) break; case DISPC_AM625: case DISPC_AM62A7: + case DISPC_AM62L: case DISPC_AM65X: case DISPC_J721E: dispc_k3_plane_init(dispc); @@ -2492,6 +2532,7 @@ static void dispc_vp_write_gamma_table(struct dispc_d= evice *dispc, break; case DISPC_AM625: case DISPC_AM62A7: + case DISPC_AM62L: case DISPC_AM65X: dispc_am65x_vp_write_gamma_table(dispc, hw_videoport); break; diff --git a/drivers/gpu/drm/tidss/tidss_dispc.h b/drivers/gpu/drm/tidss/ti= dss_dispc.h index 72a0146e57d5..28958514b8f5 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.h +++ b/drivers/gpu/drm/tidss/tidss_dispc.h @@ -67,6 +67,7 @@ enum dispc_vp_bus_type { enum dispc_dss_subrevision { DISPC_K2G, DISPC_AM625, + DISPC_AM62L, DISPC_AM62A7, DISPC_AM65X, DISPC_J721E, @@ -96,6 +97,7 @@ struct dispc_features { extern const struct dispc_features dispc_k2g_feats; extern const struct dispc_features dispc_am625_feats; extern const struct dispc_features dispc_am62a7_feats; +extern const struct dispc_features dispc_am62l_feats; extern const struct dispc_features dispc_am65x_feats; extern const struct dispc_features dispc_j721e_feats; =20 diff --git a/drivers/gpu/drm/tidss/tidss_drv.c b/drivers/gpu/drm/tidss/tids= s_drv.c index d4652e8cc28c..f2a4f659f574 100644 --- a/drivers/gpu/drm/tidss/tidss_drv.c +++ b/drivers/gpu/drm/tidss/tidss_drv.c @@ -242,6 +242,7 @@ static const struct of_device_id tidss_of_table[] =3D { { .compatible =3D "ti,k2g-dss", .data =3D &dispc_k2g_feats, }, { .compatible =3D "ti,am625-dss", .data =3D &dispc_am625_feats, }, { .compatible =3D "ti,am62a7-dss", .data =3D &dispc_am62a7_feats, }, + { .compatible =3D "ti,am62l-dss", .data =3D &dispc_am62l_feats, }, { .compatible =3D "ti,am65x-dss", .data =3D &dispc_am65x_feats, }, { .compatible =3D "ti,j721e-dss", .data =3D &dispc_j721e_feats, }, { } --=20 2.39.1