On 4/28/25 2:43 PM, Robert Richter wrote:
> There are various configuration cases of HDM decoder registers causing
> different code paths. Add comments to cxl_hdm_decode_init() to better
> explain them.
>
> Signed-off-by: Robert Richter <rrichter@amd.com>
> Reviewed-by: Gregory Price <gourry@gourry.net>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Reviewed-by: Alison Schofield <alison.schofield@intel.com>
> Reviewed-by: Fabio M. De Francesco <fabio.m.de.francesco@linux.intel.com>
> Tested-by: Gregory Price <gourry@gourry.net>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> ---
> drivers/cxl/core/pci.c | 31 ++++++++++++++++++++++---------
> 1 file changed, 22 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> index 6386e84e51a4..80bfd8ca4f8d 100644
> --- a/drivers/cxl/core/pci.c
> +++ b/drivers/cxl/core/pci.c
> @@ -416,9 +416,19 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm,
> if (global_ctrl & CXL_HDM_DECODER_ENABLE || (!hdm && info->mem_enabled))
> return devm_cxl_enable_mem(&port->dev, cxlds);
>
> + /*
> + * If the HDM Decoder Capability does not exist and DVSEC was
> + * not setup, the DVSEC based emulation cannot be used.
> + */
> if (!hdm)
> return -ENODEV;
>
> + /* The HDM Decoder Capability exists but is globally disabled. */
> +
> + /*
> + * If the DVSEC CXL Range registers are not enabled, just
> + * enable and use the HDM Decoder Capability registers.
> + */
> if (!info->mem_enabled) {
> rc = devm_cxl_enable_hdm(&port->dev, cxlhdm);
> if (rc)
> @@ -427,6 +437,18 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm,
> return devm_cxl_enable_mem(&port->dev, cxlds);
> }
>
> + /*
> + * Per CXL 2.0 Section 8.1.3.8.3 and 8.1.3.8.4 DVSEC CXL Range 1 Base
> + * [High,Low] when HDM operation is enabled the range register values
> + * are ignored by the device, but the spec also recommends matching the
> + * DVSEC Range 1,2 to HDM Decoder Range 0,1. So, non-zero info->ranges
> + * are expected even though Linux does not require or maintain that
> + * match. Check if at least one DVSEC range is enabled and allowed by
> + * the platform. That is, the DVSEC range must be covered by a locked
> + * platform window (CFMWS). Fail otherwise as the endpoint's decoders
> + * cannot be used.
> + */
> +
> root = to_cxl_port(port->dev.parent);
> while (!is_cxl_root(root) && is_cxl_port(root->dev.parent))
> root = to_cxl_port(root->dev.parent);
> @@ -454,15 +476,6 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm,
> return -ENXIO;
> }
>
> - /*
> - * Per CXL 2.0 Section 8.1.3.8.3 and 8.1.3.8.4 DVSEC CXL Range 1 Base
> - * [High,Low] when HDM operation is enabled the range register values
> - * are ignored by the device, but the spec also recommends matching the
> - * DVSEC Range 1,2 to HDM Decoder Range 0,1. So, non-zero info->ranges
> - * are expected even though Linux does not require or maintain that
> - * match. If at least one DVSEC range is enabled and allowed, skip HDM
> - * Decoder Capability Enable.
> - */
> return 0;
> }
> EXPORT_SYMBOL_NS_GPL(cxl_hdm_decode_init, "CXL");