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De Francesco" , Terry Bowman , Robert Richter Subject: [PATCH v5 03/14] cxl/pci: Add comments to cxl_hdm_decode_init() Date: Mon, 28 Apr 2025 23:43:06 +0200 Message-ID: <20250428214318.1682212-4-rrichter@amd.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250428214318.1682212-1-rrichter@amd.com> References: <20250428214318.1682212-1-rrichter@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000989E7:EE_|DS7PR12MB6072:EE_ X-MS-Office365-Filtering-Correlation-Id: 592b86bd-b559-4cfa-3647-08dd869dc10a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|7416014|1800799024|36860700013|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?mWsJyl/RTKtVDfdurR0XlBGuaIY1KsM80zcotcPCZRyIK2xBgfuGBZD89iew?= =?us-ascii?Q?QQmw7qDVLJLFBYj39gdAktBzOZh5Rv9s+y8cxK1HK50FiLFWjjggjSZi2+0p?= =?us-ascii?Q?jyTI/i5anH7ewZzQ12AfA9degU/CSzjMPJ+iXieMJ+VSYsTheonGOxdmYtxv?= =?us-ascii?Q?MC7Pg9My+3TYBQ27WRGIp/WsS2dSvXOWyyqcvhHW0vyYyfy+qOoVmdSHbbnM?= =?us-ascii?Q?ZLEdHaHltMUFKMsgATWXKuQVFNSfmD5UYGrBeH6KFVZX2EtQ+2axXGd9ZzjT?= =?us-ascii?Q?2auhqH9oWG1MHfIQe3ndJf6xV9qASEdwxJqV4OtslNd6NovocJeniZ40Ek7G?= =?us-ascii?Q?MUe4Zcaj00am7rJLJ3fnJ6yFIbE8YKjrZaBIM6FScC2ao0VLJFOApOez7+1t?= =?us-ascii?Q?IfiFLdRSLpS9KgCtH1twTG8h4OgeC+SlrCzyLbN8dEZHZ/nfZYgi0wdYOk8b?= =?us-ascii?Q?ZwP8YAuWZbTa3G9c/GPCxkSZDz74WD4XlYON8V3BwPnp9sR1vPgsac3Dg9HJ?= =?us-ascii?Q?iLOzDgBTYewrLH2dRFusj6Q8OKCHcVgLYPw7UN0BuDS+jh9/6AvvjA0Yoiiz?= =?us-ascii?Q?y6odicJaO6Kb8rIFWckJQo1A6qjDObwI9qo0RH2NpggwL8RMQcFsamZcdbOg?= =?us-ascii?Q?lhTZMvU4fcR9ZSBn8sImIEJPZKJ/X67wtWVrq0NkoUzRqgzKY1sELM7Xwccu?= =?us-ascii?Q?ewAPhNFxlB5xExr1xVtx3f9h3xocdWincrdsjlHNjsdNeR0p2xE9sz93Lxmr?= =?us-ascii?Q?i25kUS2mKXTLGQSRdMk48a/IHkIe3H7Yq2t/azOWKOBltpa0c3jT8Ib4k3er?= =?us-ascii?Q?MwivrBqxfP+PHzUnSURLahJtfSuJKNR1+Vdxoq/bGsPcA/Pd8xivE1aPRaMv?= =?us-ascii?Q?egNp0wuHj8GhUWQcEPf6yu4TjH3mKMu50rj+sto73gVJMNlx0e0W0CKF0Sps?= =?us-ascii?Q?PYrTDmxTHAV04ZWIpHRJrWfqe8nJQlf7sPBUU8II2spko4nwKXKztotEsAx0?= =?us-ascii?Q?00loGfcBmwIJTDw3aYgHDE6LD8in4Bt5sWKbi1vT0rBvrJliBcCUvV5MFgIj?= =?us-ascii?Q?rlXZE5XMsAciiXbQ3gLcxKd0AJu6QLQ3S4RX1TSKtEfityYWc4T+ORaIw9Ch?= =?us-ascii?Q?Mmb96egVbM5a1uPMRohUUUvpOjOS5GSdBQg8G4t1iDzh4QZv9X1SXo1IiYAk?= =?us-ascii?Q?XvgcLHFD7iSc4rAdZXjfyB+LN2bt7m6bR5PCWOxijkK4gMT8X8aNrlm+QZDw?= =?us-ascii?Q?7AxJTr1n1j5BDt8N0bZpTth0sWIqZla33F97jHdUkkYTgTt3oOkIY2MBYL3/?= =?us-ascii?Q?vkbCQEW6b71W0qPMzGYmbKPKibC4ukoiPPnGqfAigbYIVdQCOeCeExLAOof4?= =?us-ascii?Q?Sx1gvsUermQXekqkoFct4qluIfPItF9HSbqyK5KWLxBp3XZU73Rv3X76ddpT?= =?us-ascii?Q?XhV8TbkC+U5ZbhWBdCHV/Y9cwijH0gTUjUYI6YyUDIjGvgoqmvnzYYoaNCtt?= =?us-ascii?Q?5CXjnlWF3ao0PMxPq/YxNmVc4vKD6kknKZWH?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(376014)(7416014)(1800799024)(36860700013)(7053199007);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Apr 2025 21:43:46.1601 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 592b86bd-b559-4cfa-3647-08dd869dc10a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000989E7.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6072 Content-Type: text/plain; charset="utf-8" There are various configuration cases of HDM decoder registers causing different code paths. Add comments to cxl_hdm_decode_init() to better explain them. Signed-off-by: Robert Richter Reviewed-by: Gregory Price Reviewed-by: Jonathan Cameron Reviewed-by: Alison Schofield Reviewed-by: Fabio M. De Francesco Tested-by: Gregory Price Reviewed-by: Dave Jiang --- drivers/cxl/core/pci.c | 31 ++++++++++++++++++++++--------- 1 file changed, 22 insertions(+), 9 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 6386e84e51a4..80bfd8ca4f8d 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -416,9 +416,19 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, s= truct cxl_hdm *cxlhdm, if (global_ctrl & CXL_HDM_DECODER_ENABLE || (!hdm && info->mem_enabled)) return devm_cxl_enable_mem(&port->dev, cxlds); =20 + /* + * If the HDM Decoder Capability does not exist and DVSEC was + * not setup, the DVSEC based emulation cannot be used. + */ if (!hdm) return -ENODEV; =20 + /* The HDM Decoder Capability exists but is globally disabled. */ + + /* + * If the DVSEC CXL Range registers are not enabled, just + * enable and use the HDM Decoder Capability registers. + */ if (!info->mem_enabled) { rc =3D devm_cxl_enable_hdm(&port->dev, cxlhdm); if (rc) @@ -427,6 +437,18 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, s= truct cxl_hdm *cxlhdm, return devm_cxl_enable_mem(&port->dev, cxlds); } =20 + /* + * Per CXL 2.0 Section 8.1.3.8.3 and 8.1.3.8.4 DVSEC CXL Range 1 Base + * [High,Low] when HDM operation is enabled the range register values + * are ignored by the device, but the spec also recommends matching the + * DVSEC Range 1,2 to HDM Decoder Range 0,1. So, non-zero info->ranges + * are expected even though Linux does not require or maintain that + * match. Check if at least one DVSEC range is enabled and allowed by + * the platform. That is, the DVSEC range must be covered by a locked + * platform window (CFMWS). Fail otherwise as the endpoint's decoders + * cannot be used. + */ + root =3D to_cxl_port(port->dev.parent); while (!is_cxl_root(root) && is_cxl_port(root->dev.parent)) root =3D to_cxl_port(root->dev.parent); @@ -454,15 +476,6 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, s= truct cxl_hdm *cxlhdm, return -ENXIO; } =20 - /* - * Per CXL 2.0 Section 8.1.3.8.3 and 8.1.3.8.4 DVSEC CXL Range 1 Base - * [High,Low] when HDM operation is enabled the range register values - * are ignored by the device, but the spec also recommends matching the - * DVSEC Range 1,2 to HDM Decoder Range 0,1. So, non-zero info->ranges - * are expected even though Linux does not require or maintain that - * match. If at least one DVSEC range is enabled and allowed, skip HDM - * Decoder Capability Enable. - */ return 0; } EXPORT_SYMBOL_NS_GPL(cxl_hdm_decode_init, "CXL"); --=20 2.39.5