Add a common DT schema for DPLL device and its associated pins.
The DPLL (device phase-locked loop) is a device used for precise clock
synchronization in networking and telecom hardware.
The device includes one or more DPLLs (channels) and one or more
physical input/output pins.
Each DPLL channel is used either to provide a pulse-per-clock signal or
to drive an Ethernet equipment clock.
The input and output pins have the following properties:
* label: specifies board label
* connection type: specifies its usage depending on wiring
* list of supported or allowed frequencies: depending on how the pin
is connected and where)
* embedded sync capability: indicates whether the pin supports this
Check:
$ make dt_binding_check DT_SCHEMA_FILES=/dpll/
SCHEMA Documentation/devicetree/bindings/processed-schema.json
/home/cera/devel/kernel/linux-2.6/Documentation/devicetree/bindings/net/snps,dwmac.yaml: mac-mode: missing type definition
CHKDT ./Documentation/devicetree/bindings
LINT ./Documentation/devicetree/bindings
DTEX Documentation/devicetree/bindings/dpll/dpll-pin.example.dts
DTC [C] Documentation/devicetree/bindings/dpll/dpll-pin.example.dtb
DTEX Documentation/devicetree/bindings/dpll/dpll-device.example.dts
DTC [C] Documentation/devicetree/bindings/dpll/dpll-device.example.dtb
Signed-off-by: Ivan Vecera <ivecera@redhat.com>
---
v3->v4:
* dropped $Ref from dpll-pin reg property
* added maxItems to dpll-pin reg property
* fixed paragraph in dpll-pin desc
* dpll-pin type property renamed to connection-type
v1->v3:
* rewritten description for both device and pin
* dropped num-dplls property
* supported-frequencies property renamed to supported-frequencies-hz
---
.../devicetree/bindings/dpll/dpll-device.yaml | 76 +++++++++++++++++++
.../devicetree/bindings/dpll/dpll-pin.yaml | 45 +++++++++++
MAINTAINERS | 2 +
3 files changed, 123 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dpll/dpll-device.yaml
create mode 100644 Documentation/devicetree/bindings/dpll/dpll-pin.yaml
diff --git a/Documentation/devicetree/bindings/dpll/dpll-device.yaml b/Documentation/devicetree/bindings/dpll/dpll-device.yaml
new file mode 100644
index 0000000000000..fb8d7a9a3693f
--- /dev/null
+++ b/Documentation/devicetree/bindings/dpll/dpll-device.yaml
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dpll/dpll-device.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Digital Phase-Locked Loop (DPLL) Device
+
+maintainers:
+ - Ivan Vecera <ivecera@redhat.com>
+
+description:
+ Digital Phase-Locked Loop (DPLL) device is used for precise clock
+ synchronization in networking and telecom hardware. The device can
+ have one or more channels (DPLLs) and one or more physical input and
+ output pins. Each DPLL channel can either produce pulse-per-clock signal
+ or drive ethernet equipment clock. The type of each channel can be
+ indicated by dpll-types property.
+
+properties:
+ $nodename:
+ pattern: "^dpll(@.*)?$"
+
+ "#address-cells":
+ const: 0
+
+ "#size-cells":
+ const: 0
+
+ dpll-types:
+ description: List of DPLL channel types, one per DPLL instance.
+ $ref: /schemas/types.yaml#/definitions/non-unique-string-array
+ items:
+ enum: [pps, eec]
+
+ input-pins:
+ type: object
+ description: DPLL input pins
+ unevaluatedProperties: false
+
+ properties:
+ "#address-cells":
+ const: 1
+ "#size-cells":
+ const: 0
+
+ patternProperties:
+ "^pin@[0-9a-f]+$":
+ $ref: /schemas/dpll/dpll-pin.yaml
+ unevaluatedProperties: false
+
+ required:
+ - "#address-cells"
+ - "#size-cells"
+
+ output-pins:
+ type: object
+ description: DPLL output pins
+ unevaluatedProperties: false
+
+ properties:
+ "#address-cells":
+ const: 1
+ "#size-cells":
+ const: 0
+
+ patternProperties:
+ "^pin@[0-9]+$":
+ $ref: /schemas/dpll/dpll-pin.yaml
+ unevaluatedProperties: false
+
+ required:
+ - "#address-cells"
+ - "#size-cells"
+
+additionalProperties: true
diff --git a/Documentation/devicetree/bindings/dpll/dpll-pin.yaml b/Documentation/devicetree/bindings/dpll/dpll-pin.yaml
new file mode 100644
index 0000000000000..51db93b77306f
--- /dev/null
+++ b/Documentation/devicetree/bindings/dpll/dpll-pin.yaml
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dpll/dpll-pin.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: DPLL Pin
+
+maintainers:
+ - Ivan Vecera <ivecera@redhat.com>
+
+description: |
+ The DPLL pin is either a physical input or output pin that is provided
+ by a DPLL( Digital Phase-Locked Loop) device. The pin is identified by
+ its physical order number that is stored in reg property and can have
+ an additional set of properties like supported (allowed) frequencies,
+ label, type and may support embedded sync.
+
+ Note that the pin in this context has nothing to do with pinctrl.
+
+properties:
+ reg:
+ description: Hardware index of the DPLL pin.
+ maxItems: 1
+
+ connection-type:
+ description: Connection type of the pin
+ $ref: /schemas/types.yaml#/definitions/string
+ enum: [ext, gnss, int, mux, synce]
+
+ esync-control:
+ description: Indicates whether the pin supports embedded sync functionality.
+ type: boolean
+
+ label:
+ description: String exposed as the pin board label
+ $ref: /schemas/types.yaml#/definitions/string
+
+ supported-frequencies-hz:
+ description: List of supported frequencies for this pin, expressed in Hz.
+
+required:
+ - reg
+
+additionalProperties: false
diff --git a/MAINTAINERS b/MAINTAINERS
index 82e4b96030df5..b815e02987f3c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7188,6 +7188,8 @@ M: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
M: Jiri Pirko <jiri@resnulli.us>
L: netdev@vger.kernel.org
S: Supported
+F: Documentation/devicetree/bindings/dpll/dpll-device.yaml
+F: Documentation/devicetree/bindings/dpll/dpll-pin.yaml
F: Documentation/driver-api/dpll.rst
F: drivers/dpll/*
F: include/linux/dpll.h
--
2.49.0On Thu, Apr 24, 2025 at 05:47:15PM GMT, Ivan Vecera wrote: > Add a common DT schema for DPLL device and its associated pins. > The DPLL (device phase-locked loop) is a device used for precise clock > synchronization in networking and telecom hardware. > > The device includes one or more DPLLs (channels) and one or more > physical input/output pins. > > Each DPLL channel is used either to provide a pulse-per-clock signal or > to drive an Ethernet equipment clock. > > The input and output pins have the following properties: > * label: specifies board label > * connection type: specifies its usage depending on wiring > * list of supported or allowed frequencies: depending on how the pin > is connected and where) > * embedded sync capability: indicates whether the pin supports this > > Check: This does not belong to commit msg. You do not add compile commands of C files, do you? Whatever you want to inform and is not relevant in the Git history should be in changelog part. > $ make dt_binding_check DT_SCHEMA_FILES=/dpll/ > SCHEMA Documentation/devicetree/bindings/processed-schema.json > /home/cera/devel/kernel/linux-2.6/Documentation/devicetree/bindings/net/snps,dwmac.yaml: mac-mode: missing type definition > CHKDT ./Documentation/devicetree/bindings > LINT ./Documentation/devicetree/bindings > DTEX Documentation/devicetree/bindings/dpll/dpll-pin.example.dts > DTC [C] Documentation/devicetree/bindings/dpll/dpll-pin.example.dtb > DTEX Documentation/devicetree/bindings/dpll/dpll-device.example.dts > DTC [C] Documentation/devicetree/bindings/dpll/dpll-device.example.dtb > > Signed-off-by: Ivan Vecera <ivecera@redhat.com> > --- > v3->v4: > * dropped $Ref from dpll-pin reg property > * added maxItems to dpll-pin reg property > * fixed paragraph in dpll-pin desc ... > + > +properties: > + $nodename: > + pattern: "^dpll(@.*)?$" > + > + "#address-cells": > + const: 0 > + > + "#size-cells": > + const: 0 > + > + dpll-types: > + description: List of DPLL channel types, one per DPLL instance. > + $ref: /schemas/types.yaml#/definitions/non-unique-string-array > + items: > + enum: [pps, eec] Do channels have other properties as well in general? > + > + input-pins: > + type: object > + description: DPLL input pins > + unevaluatedProperties: false Best regards, Krzysztof
On 25. 04. 25 9:39 dop., Krzysztof Kozlowski wrote: > On Thu, Apr 24, 2025 at 05:47:15PM GMT, Ivan Vecera wrote: >> Add a common DT schema for DPLL device and its associated pins. >> The DPLL (device phase-locked loop) is a device used for precise clock >> synchronization in networking and telecom hardware. >> >> The device includes one or more DPLLs (channels) and one or more >> physical input/output pins. >> >> Each DPLL channel is used either to provide a pulse-per-clock signal or >> to drive an Ethernet equipment clock. >> >> The input and output pins have the following properties: >> * label: specifies board label >> * connection type: specifies its usage depending on wiring >> * list of supported or allowed frequencies: depending on how the pin >> is connected and where) >> * embedded sync capability: indicates whether the pin supports this >> >> Check: > > This does not belong to commit msg. You do not add compile commands of C > files, do you? > > Whatever you want to inform and is not relevant in the Git history > should be in changelog part. OK >> $ make dt_binding_check DT_SCHEMA_FILES=/dpll/ >> SCHEMA Documentation/devicetree/bindings/processed-schema.json >> /home/cera/devel/kernel/linux-2.6/Documentation/devicetree/bindings/net/snps,dwmac.yaml: mac-mode: missing type definition >> CHKDT ./Documentation/devicetree/bindings >> LINT ./Documentation/devicetree/bindings >> DTEX Documentation/devicetree/bindings/dpll/dpll-pin.example.dts >> DTC [C] Documentation/devicetree/bindings/dpll/dpll-pin.example.dtb >> DTEX Documentation/devicetree/bindings/dpll/dpll-device.example.dts >> DTC [C] Documentation/devicetree/bindings/dpll/dpll-device.example.dtb >> >> Signed-off-by: Ivan Vecera <ivecera@redhat.com> >> --- >> v3->v4: >> * dropped $Ref from dpll-pin reg property >> * added maxItems to dpll-pin reg property >> * fixed paragraph in dpll-pin desc > > ... > >> + >> +properties: >> + $nodename: >> + pattern: "^dpll(@.*)?$" >> + >> + "#address-cells": >> + const: 0 >> + >> + "#size-cells": >> + const: 0 >> + >> + dpll-types: >> + description: List of DPLL channel types, one per DPLL instance. >> + $ref: /schemas/types.yaml#/definitions/non-unique-string-array >> + items: >> + enum: [pps, eec] > > Do channels have other properties as well in general? No, other characteristics should be deducible either from compatible or in runtime. >> + >> + input-pins: >> + type: object >> + description: DPLL input pins >> + unevaluatedProperties: false > > Best regards, > Krzysztof >
On 25/04/2025 11:36, Ivan Vecera wrote: >>> + const: 0 >>> + >>> + dpll-types: >>> + description: List of DPLL channel types, one per DPLL instance. >>> + $ref: /schemas/types.yaml#/definitions/non-unique-string-array >>> + items: >>> + enum: [pps, eec] >> >> Do channels have other properties as well in general? > > No, other characteristics should be deducible either from compatible or > in runtime. > OK, with fixes in commit msg: Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
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