From nobody Mon Feb 9 12:07:45 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 49CE727F731 for ; Thu, 24 Apr 2025 15:47:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.129.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745509668; cv=none; b=mhuTwtw6EhGoRhk/IlBSdRZTA/kD9PZ1TqGr5maGnsRW3n1Rph4QdHpZkCVBUveewtMfhoMyIYgAT6TQWaQdav4UAsQUx4/0xFEFa7c9J/12bj7poe6g/haaNO35RLrjKr9eOob2+Lc51XIeYVMgN92kPYskvXZNREG61oIXHrg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745509668; c=relaxed/simple; bh=qKPykZjSAnu2JfgOnSrdqT0ksobcdJbVG8/n690Xlwo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=IKw1LZhrrAkzj/VOlzI//WHjWgd4x6yndfazYuVq7pAj44BiAsBJNodKiCBvYtmhs2zSNVnfEvSwUhY4MW5WwUSLiLG+Kpy0hwCi8iz8qFIpvLz2HiZzPHs40dn4M2fiq/xJTVqwkqiOACFe60dX4Xw3Z5SrCW2Y7Dcbs8Ao+bs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=F1MoLEah; arc=none smtp.client-ip=170.10.129.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="F1MoLEah" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1745509662; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=qz0qYSSd4qC8lp6EkAJfYJT9gTaw4kOTbeYNyoSs1fE=; b=F1MoLEahlWYfotO5zv8pX4LWn6DhbTuU+gsziLgfPS2AsLRlg8XMaHeLANeTHiD9bZ3mXH J5oPUZa4gtQt0SrnZVmeb1h3EqYd9om7JlUllrFeHzY8SdYeqleaMbb9J7bKvo9l04d63J LgEUGpYq/GzfBkpJrKt6TPXfGybh0/s= Received: from mx-prod-mc-08.mail-002.prod.us-west-2.aws.redhat.com (ec2-35-165-154-97.us-west-2.compute.amazonaws.com [35.165.154.97]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-679-ZGZP8SWLOFeWgZJABr5khQ-1; Thu, 24 Apr 2025 11:47:36 -0400 X-MC-Unique: ZGZP8SWLOFeWgZJABr5khQ-1 X-Mimecast-MFC-AGG-ID: ZGZP8SWLOFeWgZJABr5khQ_1745509654 Received: from mx-prod-int-04.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-04.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.40]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 4360018004A7; Thu, 24 Apr 2025 15:47:34 +0000 (UTC) Received: from p16v.luc.cera.cz (unknown [10.44.32.28]) by mx-prod-int-04.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 364A619560AB; Thu, 24 Apr 2025 15:47:28 +0000 (UTC) From: Ivan Vecera To: netdev@vger.kernel.org Cc: Vadim Fedorenko , Arkadiusz Kubalewski , Jiri Pirko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Prathosh Satish , Lee Jones , Kees Cook , Andy Shevchenko , Andrew Morton , Michal Schmidt , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org Subject: [PATCH net-next v4 1/8] dt-bindings: dpll: Add DPLL device and pin Date: Thu, 24 Apr 2025 17:47:15 +0200 Message-ID: <20250424154722.534284-2-ivecera@redhat.com> In-Reply-To: <20250424154722.534284-1-ivecera@redhat.com> References: <20250424154722.534284-1-ivecera@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.40 Content-Type: text/plain; charset="utf-8" Add a common DT schema for DPLL device and its associated pins. The DPLL (device phase-locked loop) is a device used for precise clock synchronization in networking and telecom hardware. The device includes one or more DPLLs (channels) and one or more physical input/output pins. Each DPLL channel is used either to provide a pulse-per-clock signal or to drive an Ethernet equipment clock. The input and output pins have the following properties: * label: specifies board label * connection type: specifies its usage depending on wiring * list of supported or allowed frequencies: depending on how the pin is connected and where) * embedded sync capability: indicates whether the pin supports this Check: $ make dt_binding_check DT_SCHEMA_FILES=3D/dpll/ SCHEMA Documentation/devicetree/bindings/processed-schema.json /home/cera/devel/kernel/linux-2.6/Documentation/devicetree/bindings/net/snp= s,dwmac.yaml: mac-mode: missing type definition CHKDT ./Documentation/devicetree/bindings LINT ./Documentation/devicetree/bindings DTEX Documentation/devicetree/bindings/dpll/dpll-pin.example.dts DTC [C] Documentation/devicetree/bindings/dpll/dpll-pin.example.dtb DTEX Documentation/devicetree/bindings/dpll/dpll-device.example.dts DTC [C] Documentation/devicetree/bindings/dpll/dpll-device.example.dtb Signed-off-by: Ivan Vecera Reviewed-by: Krzysztof Kozlowski --- v3->v4: * dropped $Ref from dpll-pin reg property * added maxItems to dpll-pin reg property * fixed paragraph in dpll-pin desc * dpll-pin type property renamed to connection-type v1->v3: * rewritten description for both device and pin * dropped num-dplls property * supported-frequencies property renamed to supported-frequencies-hz --- .../devicetree/bindings/dpll/dpll-device.yaml | 76 +++++++++++++++++++ .../devicetree/bindings/dpll/dpll-pin.yaml | 45 +++++++++++ MAINTAINERS | 2 + 3 files changed, 123 insertions(+) create mode 100644 Documentation/devicetree/bindings/dpll/dpll-device.yaml create mode 100644 Documentation/devicetree/bindings/dpll/dpll-pin.yaml diff --git a/Documentation/devicetree/bindings/dpll/dpll-device.yaml b/Docu= mentation/devicetree/bindings/dpll/dpll-device.yaml new file mode 100644 index 0000000000000..fb8d7a9a3693f --- /dev/null +++ b/Documentation/devicetree/bindings/dpll/dpll-device.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dpll/dpll-device.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Digital Phase-Locked Loop (DPLL) Device + +maintainers: + - Ivan Vecera + +description: + Digital Phase-Locked Loop (DPLL) device is used for precise clock + synchronization in networking and telecom hardware. The device can + have one or more channels (DPLLs) and one or more physical input and + output pins. Each DPLL channel can either produce pulse-per-clock signal + or drive ethernet equipment clock. The type of each channel can be + indicated by dpll-types property. + +properties: + $nodename: + pattern: "^dpll(@.*)?$" + + "#address-cells": + const: 0 + + "#size-cells": + const: 0 + + dpll-types: + description: List of DPLL channel types, one per DPLL instance. + $ref: /schemas/types.yaml#/definitions/non-unique-string-array + items: + enum: [pps, eec] + + input-pins: + type: object + description: DPLL input pins + unevaluatedProperties: false + + properties: + "#address-cells": + const: 1 + "#size-cells": + const: 0 + + patternProperties: + "^pin@[0-9a-f]+$": + $ref: /schemas/dpll/dpll-pin.yaml + unevaluatedProperties: false + + required: + - "#address-cells" + - "#size-cells" + + output-pins: + type: object + description: DPLL output pins + unevaluatedProperties: false + + properties: + "#address-cells": + const: 1 + "#size-cells": + const: 0 + + patternProperties: + "^pin@[0-9]+$": + $ref: /schemas/dpll/dpll-pin.yaml + unevaluatedProperties: false + + required: + - "#address-cells" + - "#size-cells" + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/dpll/dpll-pin.yaml b/Documen= tation/devicetree/bindings/dpll/dpll-pin.yaml new file mode 100644 index 0000000000000..51db93b77306f --- /dev/null +++ b/Documentation/devicetree/bindings/dpll/dpll-pin.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dpll/dpll-pin.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: DPLL Pin + +maintainers: + - Ivan Vecera + +description: | + The DPLL pin is either a physical input or output pin that is provided + by a DPLL( Digital Phase-Locked Loop) device. The pin is identified by + its physical order number that is stored in reg property and can have + an additional set of properties like supported (allowed) frequencies, + label, type and may support embedded sync. + + Note that the pin in this context has nothing to do with pinctrl. + +properties: + reg: + description: Hardware index of the DPLL pin. + maxItems: 1 + + connection-type: + description: Connection type of the pin + $ref: /schemas/types.yaml#/definitions/string + enum: [ext, gnss, int, mux, synce] + + esync-control: + description: Indicates whether the pin supports embedded sync function= ality. + type: boolean + + label: + description: String exposed as the pin board label + $ref: /schemas/types.yaml#/definitions/string + + supported-frequencies-hz: + description: List of supported frequencies for this pin, expressed in = Hz. + +required: + - reg + +additionalProperties: false diff --git a/MAINTAINERS b/MAINTAINERS index 82e4b96030df5..b815e02987f3c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7188,6 +7188,8 @@ M: Arkadiusz Kubalewski M: Jiri Pirko L: netdev@vger.kernel.org S: Supported +F: Documentation/devicetree/bindings/dpll/dpll-device.yaml +F: Documentation/devicetree/bindings/dpll/dpll-pin.yaml F: Documentation/driver-api/dpll.rst F: drivers/dpll/* F: include/linux/dpll.h --=20 2.49.0