[PATCH v2 3/5] arm64: dts: ti: k3-am65-main: Add missing taps to sdhci0

Judith Mendez posted 5 patches 8 months ago
There is a newer version of this series
[PATCH v2 3/5] arm64: dts: ti: k3-am65-main: Add missing taps to sdhci0
Posted by Judith Mendez 8 months ago
For am65x, add missing ITAPDLYSEL values for Default Speed and High
Speed SDR modes to sdhci0 node according to the device datasheet [0].

Fixes: eac99d38f861 ("arm64: dts: ti: k3-am654-main: Update otap-del-sel values")
[0] https://www.ti.com/lit/gpn/am6548
Signed-off-by: Judith Mendez <jm@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index 94a812a1355ba..5ebf7ada6e485 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -449,6 +449,8 @@ sdhci0: mmc@4f80000 {
 		ti,otap-del-sel-mmc-hs = <0x0>;
 		ti,otap-del-sel-ddr52 = <0x5>;
 		ti,otap-del-sel-hs200 = <0x5>;
+		ti,itap-del-sel-legacy = <0xa>;
+		ti,itap-del-sel-mmc-hs = <0x1>;
 		ti,itap-del-sel-ddr52 = <0x0>;
 		dma-coherent;
 		status = "disabled";
-- 
2.49.0
Re: [PATCH v2 3/5] arm64: dts: ti: k3-am65-main: Add missing taps to sdhci0
Posted by Moteen Shah 7 months, 3 weeks ago
On 18/04/25 05:00, Judith Mendez wrote:
> For am65x, add missing ITAPDLYSEL values for Default Speed and High
> Speed SDR modes to sdhci0 node according to the device datasheet [0].
>
> Fixes: eac99d38f861 ("arm64: dts: ti: k3-am654-main: Update otap-del-sel values")
> [0] https://www.ti.com/lit/gpn/am6548
> Signed-off-by: Judith Mendez <jm@ti.com>
> ---
>   arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 2 ++
>   1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> index 94a812a1355ba..5ebf7ada6e485 100644
> --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> @@ -449,6 +449,8 @@ sdhci0: mmc@4f80000 {
>   		ti,otap-del-sel-mmc-hs = <0x0>;
>   		ti,otap-del-sel-ddr52 = <0x5>;
>   		ti,otap-del-sel-hs200 = <0x5>;
> +		ti,itap-del-sel-legacy = <0xa>;
> +		ti,itap-del-sel-mmc-hs = <0x1>;

Reviewed-by: Moteen Shah <m-shah@ti.com>

>   		ti,itap-del-sel-ddr52 = <0x0>;
>   		dma-coherent;
>   		status = "disabled";