.../boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 12 +++++++++--- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 10 ++++++---- 2 files changed, 15 insertions(+), 7 deletions(-)
From: Parth Pancholi <parth.pancholi@toradex.com>
TI J784S4-based devices, such as the AM69 SoC, provide PCIE_REFCLK outputs
from the SoC, which can be used to clock external PCIe endpoint devices.
Each PCIE_REFCLK output is enabled via the corresponding ACSPCIE clock
buffer, with each buffer supporting two PADs to provide reference clocks
for two associated PCIe instances. The mappings are as follows:
- PCIe0 -> ACSPCIE1 PAD0
- PCIe1 -> ACSPCIE0 PAD0
- PCIe2 -> ACSPCIE1 PAD1
- PCIe3 -> ACSPCIE0 PAD1
This patch enables each ACSPCIE module and its corresponding PADs to ensure
that all PCIE_REFCLK outputs are functional.
This change have been tested on an AM69-based custom hardware platform,
where all four PCIe instances (PCIe0, PCIe1, PCIe2, and PCIe3) with the
internal PCIE_REFCLK are utilized with various endpoint devices such as
a WiFi card, NVMe SSD, and PCIe-to-USB bridge.
Link: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1484211/am69-pcie-refclk-out-and-acspcie-mappings
Signed-off-by: Parth Pancholi <parth.pancholi@toradex.com>
---
This change depends on https://lore.kernel.org/all/20241209085157.1203168-1-s-vadapalli@ti.com/
v2: set ti,syscon-acspcie-proxy-ctrl mask to 0x3 for all PCIe instances to prevent unintended overrides.
v1: https://lore.kernel.org/all/20250320122259.525613-1-parth105105@gmail.com/
---
.../boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 12 +++++++++---
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 10 ++++++----
2 files changed, 15 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
index 591609f3194c..d82d5cb5607e 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
@@ -132,6 +132,11 @@ acspcie0_proxy_ctrl: clock-controller@1a090 {
compatible = "ti,j784s4-acspcie-proxy-ctrl", "syscon";
reg = <0x1a090 0x4>;
};
+
+ acspcie1_proxy_ctrl: clock-controller@1a094 {
+ compatible = "ti,j784s4-acspcie-proxy-ctrl", "syscon";
+ reg = <0x1a094 0x4>;
+ };
};
main_ehrpwm0: pwm@3000000 {
@@ -1067,11 +1072,12 @@ pcie0_rc: pcie@2900000 {
interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
device_type = "pci";
ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
+ ti,syscon-acspcie-proxy-ctrl = <&acspcie1_proxy_ctrl 0x3>;
max-link-speed = <3>;
num-lanes = <4>;
power-domains = <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 332 0>;
- clock-names = "fck";
+ clocks = <&k3_clks 332 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>;
+ clock-names = "fck", "pcie_refclk";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x0 0xff>;
@@ -1111,7 +1117,7 @@ pcie1_rc: pcie@2910000 {
ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
<0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
- ti,syscon-acspcie-proxy-ctrl = <&acspcie0_proxy_ctrl 0x1>;
+ ti,syscon-acspcie-proxy-ctrl = <&acspcie0_proxy_ctrl 0x3>;
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index 0160fe0da983..ebbc315649d0 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -34,8 +34,8 @@ pcie2_rc: pcie@2920000 {
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 334 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 334 0>;
- clock-names = "fck";
+ clocks = <&k3_clks 334 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>;
+ clock-names = "fck", "pcie_refclk";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x0 0xff>;
@@ -45,6 +45,7 @@ pcie2_rc: pcie@2920000 {
dma-coherent;
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
ti,syscon-pcie-ctrl = <&pcie2_ctrl 0x0>;
+ ti,syscon-acspcie-proxy-ctrl = <&acspcie1_proxy_ctrl 0x3>;
status = "disabled";
};
@@ -63,8 +64,8 @@ pcie3_rc: pcie@2930000 {
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 335 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 335 0>;
- clock-names = "fck";
+ clocks = <&k3_clks 335 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>;
+ clock-names = "fck", "pcie_refclk";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x0 0xff>;
@@ -74,6 +75,7 @@ pcie3_rc: pcie@2930000 {
dma-coherent;
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
ti,syscon-pcie-ctrl = <&pcie3_ctrl 0x0>;
+ ti,syscon-acspcie-proxy-ctrl = <&acspcie0_proxy_ctrl 0x3>;
status = "disabled";
};
--
2.34.1Thanks for patch, Parth On 4/4/2025 3:42 PM, Parth Pancholi wrote: > From: Parth Pancholi <parth.pancholi@toradex.com> > > TI J784S4-based devices, such as the AM69 SoC, provide PCIE_REFCLK outputs > from the SoC, which can be used to clock external PCIe endpoint devices. > Each PCIE_REFCLK output is enabled via the corresponding ACSPCIE clock > buffer, with each buffer supporting two PADs to provide reference clocks > for two associated PCIe instances. The mappings are as follows: > - PCIe0 -> ACSPCIE1 PAD0 > - PCIe1 -> ACSPCIE0 PAD0 > - PCIe2 -> ACSPCIE1 PAD1 > - PCIe3 -> ACSPCIE0 PAD1 > > This patch enables each ACSPCIE module and its corresponding PADs to ensure > that all PCIE_REFCLK outputs are functional. > > This change have been tested on an AM69-based custom hardware platform, > where all four PCIe instances (PCIe0, PCIe1, PCIe2, and PCIe3) with the > internal PCIE_REFCLK are utilized with various endpoint devices such as > a WiFi card, NVMe SSD, and PCIe-to-USB bridge. You can enabling REFCLK to be out as default. There are few boards, on which this clock is either terminated at test point or not connected at all Example AM69 board PCIE_REFCLK2_P_OUT is not connected and PCIE_REFCLK0_P_OUT is terminated at test points. IMO, this clock to be enabled where this can be connected to PCIe EP. Let Siddharth also share his comment, where to enable these clocks board file or SOC file. Regards Udit > Link: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1484211/am69-pcie-refclk-out-and-acspcie-mappings > Signed-off-by: Parth Pancholi <parth.pancholi@toradex.com> > --- > This change depends on https://lore.kernel.org/all/20241209085157.1203168-1-s-vadapalli@ti.com/ > v2: set ti,syscon-acspcie-proxy-ctrl mask to 0x3 for all PCIe instances to prevent unintended overrides. > v1: https://lore.kernel.org/all/20250320122259.525613-1-parth105105@gmail.com/ > --- > .../boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 12 +++++++++--- > arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 10 ++++++---- > 2 files changed, 15 insertions(+), 7 deletions(-) > [..]
On Sat, Apr 19, 2025 at 06:38:00PM +0530, Kumar, Udit wrote: > Thanks for patch, Parth > > On 4/4/2025 3:42 PM, Parth Pancholi wrote: Hello Parth, > > From: Parth Pancholi <parth.pancholi@toradex.com> > > > > TI J784S4-based devices, such as the AM69 SoC, provide PCIE_REFCLK outputs > > from the SoC, which can be used to clock external PCIe endpoint devices. > > Each PCIE_REFCLK output is enabled via the corresponding ACSPCIE clock > > buffer, with each buffer supporting two PADs to provide reference clocks > > for two associated PCIe instances. The mappings are as follows: > > - PCIe0 -> ACSPCIE1 PAD0 > > - PCIe1 -> ACSPCIE0 PAD0 > > - PCIe2 -> ACSPCIE1 PAD1 > > - PCIe3 -> ACSPCIE0 PAD1 > > > > This patch enables each ACSPCIE module and its corresponding PADs to ensure > > that all PCIE_REFCLK outputs are functional. > > > > This change have been tested on an AM69-based custom hardware platform, > > where all four PCIe instances (PCIe0, PCIe1, PCIe2, and PCIe3) with the > > internal PCIE_REFCLK are utilized with various endpoint devices such as > > a WiFi card, NVMe SSD, and PCIe-to-USB bridge. > > You can enabling REFCLK to be out as default. > > There are few boards, on which this clock is either terminated at test point > or not connected at all > > Example AM69 board > > PCIE_REFCLK2_P_OUT is not connected and PCIE_REFCLK0_P_OUT is terminated at > test points. > > > IMO, this clock to be enabled where this can be connected to PCIe EP. > > Let Siddharth also share his comment, where to enable these clocks board > file or SOC file. As Udit has pointed out, the reference clock outputs from ACSPCIE buffers should be enabled in the board files. I will be updating the patch that I had posted for enabling output of ACSPCIE0 PAD0 for PCIe1 by moving the changes to the board file k3-j784s4-j742s2-evm-common.dtsi Please update your patch accordingly. The overrides will no longer be required as the property will be defined in the board file itself for AM69. Regards, Siddharth.
On Sun, Apr 20, 2025 at 08:25:22AM +0530, Siddharth Vadapalli wrote: > On Sat, Apr 19, 2025 at 06:38:00PM +0530, Kumar, Udit wrote: > > Thanks for patch, Parth > > > > On 4/4/2025 3:42 PM, Parth Pancholi wrote: > > Hello Parth, > > > > From: Parth Pancholi <parth.pancholi@toradex.com> > > > > > > TI J784S4-based devices, such as the AM69 SoC, provide PCIE_REFCLK outputs > > > from the SoC, which can be used to clock external PCIe endpoint devices. > > > Each PCIE_REFCLK output is enabled via the corresponding ACSPCIE clock > > > buffer, with each buffer supporting two PADs to provide reference clocks > > > for two associated PCIe instances. The mappings are as follows: > > > - PCIe0 -> ACSPCIE1 PAD0 > > > - PCIe1 -> ACSPCIE0 PAD0 > > > - PCIe2 -> ACSPCIE1 PAD1 > > > - PCIe3 -> ACSPCIE0 PAD1 > > > > > > This patch enables each ACSPCIE module and its corresponding PADs to ensure > > > that all PCIE_REFCLK outputs are functional. > > > > > > This change have been tested on an AM69-based custom hardware platform, > > > where all four PCIe instances (PCIe0, PCIe1, PCIe2, and PCIe3) with the > > > internal PCIE_REFCLK are utilized with various endpoint devices such as > > > a WiFi card, NVMe SSD, and PCIe-to-USB bridge. > > > > You can enabling REFCLK to be out as default. > > > > There are few boards, on which this clock is either terminated at test point > > or not connected at all > > > > Example AM69 board > > > > PCIE_REFCLK2_P_OUT is not connected and PCIE_REFCLK0_P_OUT is terminated at > > test points. > > > > > > IMO, this clock to be enabled where this can be connected to PCIe EP. > > > > Let Siddharth also share his comment, where to enable these clocks board > > file or SOC file. > > As Udit has pointed out, the reference clock outputs from ACSPCIE > buffers should be enabled in the board files. I will be updating the > patch that I had posted for enabling output of ACSPCIE0 PAD0 for PCIe1 > by moving the changes to the board file > k3-j784s4-j742s2-evm-common.dtsi > > Please update your patch accordingly. The overrides will no longer be > required as the property will be defined in the board file itself for > AM69. I have posted the v3 series [0] which does the following: 1. Introduce the ACSPCIE0 node in the SoC file to allow reuse across: J784S4, J742S2 and AM69 2. Update 'pcie1_rc' node in the Board file specific to J784S4 and J742S2 to drive the reference clock from PAD0 of ACSPCIE0 As a result, the current patch for AM69 can be converted to a series which does the following: 1. Introduce the ACSPCIE1 node in the SoC file to allow reuse across: J784S4, J742S2 and AM69 2. Update 'pcie0_rc', 'pcie1_rc', 'pcie2_rc' and 'pcie3_rc' in the Board files to drive the reference clock from PAD0 and PAD1 of both ACSPCIE0 and ACSPCIE1 [0]: https://lore.kernel.org/r/20250422123218.3788223-1-s-vadapalli@ti.com/ Regards, Siddharth.
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