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[31.10.206.125]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec1f27a55sm43732995e9.2.2025.04.04.03.12.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Apr 2025 03:12:46 -0700 (PDT) From: Parth Pancholi To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Parth Pancholi , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2] arm64: dts: ti: k3-j784s4-main: Enable ACSPCIE outputs for PCIe interfaces Date: Fri, 4 Apr 2025 12:12:34 +0200 Message-Id: <20250404101234.2671147-1-parth105105@gmail.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Parth Pancholi TI J784S4-based devices, such as the AM69 SoC, provide PCIE_REFCLK outputs from the SoC, which can be used to clock external PCIe endpoint devices. Each PCIE_REFCLK output is enabled via the corresponding ACSPCIE clock buffer, with each buffer supporting two PADs to provide reference clocks for two associated PCIe instances. The mappings are as follows: - PCIe0 -> ACSPCIE1 PAD0 - PCIe1 -> ACSPCIE0 PAD0 - PCIe2 -> ACSPCIE1 PAD1 - PCIe3 -> ACSPCIE0 PAD1 This patch enables each ACSPCIE module and its corresponding PADs to ensure that all PCIE_REFCLK outputs are functional. This change have been tested on an AM69-based custom hardware platform, where all four PCIe instances (PCIe0, PCIe1, PCIe2, and PCIe3) with the internal PCIE_REFCLK are utilized with various endpoint devices such as a WiFi card, NVMe SSD, and PCIe-to-USB bridge. Link: https://e2e.ti.com/support/processors-group/processors/f/processors-f= orum/1484211/am69-pcie-refclk-out-and-acspcie-mappings Signed-off-by: Parth Pancholi --- This change depends on https://lore.kernel.org/all/20241209085157.1203168-1= -s-vadapalli@ti.com/ v2: set ti,syscon-acspcie-proxy-ctrl mask to 0x3 for all PCIe instances to = prevent unintended overrides. v1: https://lore.kernel.org/all/20250320122259.525613-1-parth105105@gmail.c= om/ --- .../boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 12 +++++++++--- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 10 ++++++---- 2 files changed, 15 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arc= h/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi index 591609f3194c..d82d5cb5607e 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi @@ -132,6 +132,11 @@ acspcie0_proxy_ctrl: clock-controller@1a090 { compatible =3D "ti,j784s4-acspcie-proxy-ctrl", "syscon"; reg =3D <0x1a090 0x4>; }; + + acspcie1_proxy_ctrl: clock-controller@1a094 { + compatible =3D "ti,j784s4-acspcie-proxy-ctrl", "syscon"; + reg =3D <0x1a094 0x4>; + }; }; =20 main_ehrpwm0: pwm@3000000 { @@ -1067,11 +1072,12 @@ pcie0_rc: pcie@2900000 { interrupts =3D ; device_type =3D "pci"; ti,syscon-pcie-ctrl =3D <&pcie0_ctrl 0x0>; + ti,syscon-acspcie-proxy-ctrl =3D <&acspcie1_proxy_ctrl 0x3>; max-link-speed =3D <3>; num-lanes =3D <4>; power-domains =3D <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>; - clocks =3D <&k3_clks 332 0>; - clock-names =3D "fck"; + clocks =3D <&k3_clks 332 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>; + clock-names =3D "fck", "pcie_refclk"; #address-cells =3D <3>; #size-cells =3D <2>; bus-range =3D <0x0 0xff>; @@ -1111,7 +1117,7 @@ pcie1_rc: pcie@2910000 { ranges =3D <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; dma-ranges =3D <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; - ti,syscon-acspcie-proxy-ctrl =3D <&acspcie0_proxy_ctrl 0x1>; + ti,syscon-acspcie-proxy-ctrl =3D <&acspcie0_proxy_ctrl 0x3>; status =3D "disabled"; }; =20 diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j784s4-main.dtsi index 0160fe0da983..ebbc315649d0 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -34,8 +34,8 @@ pcie2_rc: pcie@2920000 { max-link-speed =3D <3>; num-lanes =3D <2>; power-domains =3D <&k3_pds 334 TI_SCI_PD_EXCLUSIVE>; - clocks =3D <&k3_clks 334 0>; - clock-names =3D "fck"; + clocks =3D <&k3_clks 334 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>; + clock-names =3D "fck", "pcie_refclk"; #address-cells =3D <3>; #size-cells =3D <2>; bus-range =3D <0x0 0xff>; @@ -45,6 +45,7 @@ pcie2_rc: pcie@2920000 { dma-coherent; dma-ranges =3D <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; ti,syscon-pcie-ctrl =3D <&pcie2_ctrl 0x0>; + ti,syscon-acspcie-proxy-ctrl =3D <&acspcie1_proxy_ctrl 0x3>; status =3D "disabled"; }; =20 @@ -63,8 +64,8 @@ pcie3_rc: pcie@2930000 { max-link-speed =3D <3>; num-lanes =3D <2>; power-domains =3D <&k3_pds 335 TI_SCI_PD_EXCLUSIVE>; - clocks =3D <&k3_clks 335 0>; - clock-names =3D "fck"; + clocks =3D <&k3_clks 335 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>; + clock-names =3D "fck", "pcie_refclk"; #address-cells =3D <3>; #size-cells =3D <2>; bus-range =3D <0x0 0xff>; @@ -74,6 +75,7 @@ pcie3_rc: pcie@2930000 { dma-coherent; dma-ranges =3D <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; ti,syscon-pcie-ctrl =3D <&pcie3_ctrl 0x0>; + ti,syscon-acspcie-proxy-ctrl =3D <&acspcie0_proxy_ctrl 0x3>; status =3D "disabled"; }; =20 --=20 2.34.1