Hello all,

Now that we have ti,j784s4-pcie-ctrl[0] let's use it. This makes these
K3 SoCs all match what is already done for J784s4.

No functional change, DT changes are fully backwards and forwards
compatible.

[0]: commit cc1965b02d6c ("dt-bindings: mfd: syscon: Add ti,j784s4-pcie-ctrl compatible")
<https://lore.kernel.org/all/20240204090336.3209063-1-s-vadapalli@ti.com/>

Posting next revision for PCIe control node cleanup with minor changes
to new overlays added after v1 was posted.

NOTE: Once the bindings are in the mainline tree, scm_conf will be
converted to "simple-bus" compatible which will unblock other
items like audio_refclk in scm_conf required for audio support
for TI SoC J721S2-EVM (currently giving dtbs_check warnings)

v1: <https://lore.kernel.org/all/20241016233044.240699-1-afd@ti.com/>

Changelog v1->v2:
- Change property description and add example in the binding
- Add changes in additional overlays using pcie*_ctrl node

Andrew Davis (5):
  dt-bindings: soc: ti: ti,j721e-system-controller: Add PCIe ctrl
    property
  arm64: dts: ti: k3-j721e: Add PCIe ctrl node to scm_conf region
  arm64: dts: ti: k3-j7200: Add PCIe ctrl node to scm_conf region
  arm64: dts: ti: k3-j721s2: Add PCIe ctrl node to scm_conf region
  arm64: dts: ti: k3-am64: Add PCIe ctrl node to main_conf region

 .../soc/ti/ti,j721e-system-controller.yaml    | 10 +++++++
 arch/arm64/boot/dts/ti/k3-am64-main.dtsi      |  7 ++++-
 .../boot/dts/ti/k3-am642-evm-pcie0-ep.dtso    |  2 +-
 .../ti/k3-am68-sk-base-board-pcie1-ep.dtso    |  2 +-
 .../boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso    |  2 +-
 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi     |  7 ++++-
 .../boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso    |  2 +-
 .../boot/dts/ti/k3-j721e-evm-pcie1-ep.dtso    |  2 +-
 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi     | 28 ++++++++++++++++---
 .../boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso   |  2 +-
 arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi    |  7 ++++-
 11 files changed, 58 insertions(+), 13 deletions(-)

-- 
2.34.1

Hi Jayesh Choudhary,

On Wed, 02 Apr 2025 17:01:56 +0530, Jayesh Choudhary wrote:
> Now that we have ti,j784s4-pcie-ctrl[0] let's use it. This makes these
> K3 SoCs all match what is already done for J784s4.
> 
> No functional change, DT changes are fully backwards and forwards
> compatible.
> 
> [0]: commit cc1965b02d6c ("dt-bindings: mfd: syscon: Add ti,j784s4-pcie-ctrl compatible")
> <https://lore.kernel.org/all/20240204090336.3209063-1-s-vadapalli@ti.com/>
> 
> [...]

I have applied the following to branch ti-k3-dts-next on [1].
Thank you!

[1/5] dt-bindings: soc: ti: ti,j721e-system-controller: Add PCIe ctrl property
      commit: c574db0b68a600f9548f0ef7bcba723562713587
[2/5] arm64: dts: ti: k3-j721e: Add PCIe ctrl node to scm_conf region
      commit: df2210b2da139e3a733bd7bd1406cd74d39d59a7
[3/5] arm64: dts: ti: k3-j7200: Add PCIe ctrl node to scm_conf region
      commit: 1f326fb84a6074772f01dc63ed4d3eb791682479
[4/5] arm64: dts: ti: k3-j721s2: Add PCIe ctrl node to scm_conf region
      commit: 755e47a71f9dbfbdb33fc18d20a74b7804a20acf
[5/5] arm64: dts: ti: k3-am64: Add PCIe ctrl node to main_conf region
      commit: 4e7ad3b4464571d7bec6869944151b27cce44435

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
-- 
Regards,
Nishanth Menon
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