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From: Jayesh Choudhary <j-choudhary@ti.com>
To: <robh@kernel.org>, <krzk+dt@kernel.org>, <conor+dt@kernel.org>,
<nm@ti.com>, <vigneshr@ti.com>, <afd@ti.com>, <s-vadapalli@ti.com>,
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Subject: [PATCH v2 1/5] dt-bindings: soc: ti: ti,j721e-system-controller: Add
PCIe ctrl property
Date: Wed, 2 Apr 2025 17:01:57 +0530
Message-ID: <20250402113201.151195-2-j-choudhary@ti.com>
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From: Andrew Davis <afd@ti.com>
Add a pattern property for pcie-ctrl which can be part of this controller.
Signed-off-by: Andrew Davis <afd@ti.com>
[j-choudhary@ti.com: Change description and add example]
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
.../bindings/soc/ti/ti,j721e-system-controller.yaml | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-contr=
oller.yaml b/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-contr=
oller.yaml
index 378e9cc5fac2..13b6b6fa5dee 100644
--- a/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.y=
aml
+++ b/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.y=
aml
@@ -68,6 +68,11 @@ patternProperties:
description:
The node corresponding to SoC chip identification.
=20
+ "^pcie-ctrl@[0-9a-f]+$":
+ type: object
+ description:
+ The node corresponding to PCIe control register.
+
required:
- compatible
- reg
@@ -110,5 +115,10 @@ examples:
compatible =3D "ti,am654-chipid";
reg =3D <0x14 0x4>;
};
+
+ pcie0_ctrl: pcie-ctrl@4070 {
+ compatible =3D "ti,j784s4-pcie-ctrl", "syscon";
+ reg =3D <0x4070 0x4>;
+ };
};
...
--=20
2.34.1
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From: Jayesh Choudhary <j-choudhary@ti.com>
To: <robh@kernel.org>, <krzk+dt@kernel.org>, <conor+dt@kernel.org>,
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Subject: [PATCH v2 2/5] arm64: dts: ti: k3-j721e: Add PCIe ctrl node to
scm_conf region
Date: Wed, 2 Apr 2025 17:01:58 +0530
Message-ID: <20250402113201.151195-3-j-choudhary@ti.com>
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From: Andrew Davis <afd@ti.com>
This region is used for controlling the function of the PCIe IP. It is
compatible with "ti,j784s4-pcie-ctrl", add this here and use it with
the PCIe nodes.
Signed-off-by: Andrew Davis <afd@ti.com>
[j-choudhary@ti.com: Add changes to k3-j721e-evm-pcie1-ep.dtso]
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
.../boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso | 2 +-
.../boot/dts/ti/k3-j721e-evm-pcie1-ep.dtso | 2 +-
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 28 ++++++++++++++++---
3 files changed, 26 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso b/arch/arm64=
/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso
index 4062709d6579..a8a502a6207f 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso
+++ b/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso
@@ -38,7 +38,7 @@ pcie0_ep: pcie-ep@2900000 {
reg-names =3D "intd_cfg", "user_cfg", "reg", "mem";
interrupt-names =3D "link_state";
interrupts =3D <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
- ti,syscon-pcie-ctrl =3D <&scm_conf 0x4070>;
+ ti,syscon-pcie-ctrl =3D <&pcie0_ctrl 0x0>;
max-link-speed =3D <3>;
num-lanes =3D <1>;
power-domains =3D <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie1-ep.dtso b/arch/arm64=
/boot/dts/ti/k3-j721e-evm-pcie1-ep.dtso
index a8cccdcf3e3b..436085157a69 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie1-ep.dtso
+++ b/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie1-ep.dtso
@@ -48,6 +48,6 @@ pcie1_ep: pcie-ep@2910000 {
dma-coherent;
phys =3D <&serdes1_pcie_link>;
phy-names =3D "pcie-phy";
- ti,syscon-pcie-ctrl =3D <&scm_conf 0x4074>;
+ ti,syscon-pcie-ctrl =3D <&pcie1_ctrl 0x0>;
};
};
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dt=
s/ti/k3-j721e-main.dtsi
index af3d730154ac..d7263ad43163 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -44,6 +44,26 @@ scm_conf: scm-conf@100000 {
#size-cells =3D <1>;
ranges =3D <0x0 0x0 0x00100000 0x1c000>;
=20
+ pcie0_ctrl: pcie-ctrl@4070 {
+ compatible =3D "ti,j784s4-pcie-ctrl", "syscon";
+ reg =3D <0x4070 0x4>;
+ };
+
+ pcie1_ctrl: pcie-ctrl@4074 {
+ compatible =3D "ti,j784s4-pcie-ctrl", "syscon";
+ reg =3D <0x4074 0x4>;
+ };
+
+ pcie2_ctrl: pcie-ctrl@4078 {
+ compatible =3D "ti,j784s4-pcie-ctrl", "syscon";
+ reg =3D <0x4078 0x4>;
+ };
+
+ pcie3_ctrl: pcie-ctrl@407c {
+ compatible =3D "ti,j784s4-pcie-ctrl", "syscon";
+ reg =3D <0x407c 0x4>;
+ };
+
serdes_ln_ctrl: mux-controller@4080 {
compatible =3D "reg-mux";
reg =3D <0x4080 0x50>;
@@ -946,7 +966,7 @@ pcie0_rc: pcie@2900000 {
interrupt-names =3D "link_state";
interrupts =3D <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
device_type =3D "pci";
- ti,syscon-pcie-ctrl =3D <&scm_conf 0x4070>;
+ ti,syscon-pcie-ctrl =3D <&pcie0_ctrl 0x0>;
max-link-speed =3D <3>;
num-lanes =3D <2>;
power-domains =3D <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
@@ -975,7 +995,7 @@ pcie1_rc: pcie@2910000 {
interrupt-names =3D "link_state";
interrupts =3D <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
device_type =3D "pci";
- ti,syscon-pcie-ctrl =3D <&scm_conf 0x4074>;
+ ti,syscon-pcie-ctrl =3D <&pcie1_ctrl 0x0>;
max-link-speed =3D <3>;
num-lanes =3D <2>;
power-domains =3D <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
@@ -1004,7 +1024,7 @@ pcie2_rc: pcie@2920000 {
interrupt-names =3D "link_state";
interrupts =3D <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
device_type =3D "pci";
- ti,syscon-pcie-ctrl =3D <&scm_conf 0x4078>;
+ ti,syscon-pcie-ctrl =3D <&pcie2_ctrl 0x0>;
max-link-speed =3D <3>;
num-lanes =3D <2>;
power-domains =3D <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
@@ -1033,7 +1053,7 @@ pcie3_rc: pcie@2930000 {
interrupt-names =3D "link_state";
interrupts =3D <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
device_type =3D "pci";
- ti,syscon-pcie-ctrl =3D <&scm_conf 0x407c>;
+ ti,syscon-pcie-ctrl =3D <&pcie3_ctrl 0x0>;
max-link-speed =3D <3>;
num-lanes =3D <2>;
power-domains =3D <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
--=20
2.34.1
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To: <robh@kernel.org>, <krzk+dt@kernel.org>, <conor+dt@kernel.org>,
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Subject: [PATCH v2 3/5] arm64: dts: ti: k3-j7200: Add PCIe ctrl node to
scm_conf region
Date: Wed, 2 Apr 2025 17:01:59 +0530
Message-ID: <20250402113201.151195-4-j-choudhary@ti.com>
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From: Andrew Davis <afd@ti.com>
This region is used for controlling the function of the PCIe IP. It is
compatible with "ti,j784s4-pcie-ctrl", add this here and use it with
the PCIe node.
Signed-off-by: Andrew Davis <afd@ti.com>
[j-choudhary@ti.com: Add changes to k3-j7200-evm-pcie1-ep.dtso]
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso | 2 +-
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 7 ++++++-
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso b/arch/arm64=
/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso
index 3cc315a0e084..281076d905f3 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso
+++ b/arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso
@@ -48,6 +48,6 @@ pcie1_ep: pcie-ep@2910000 {
dma-coherent;
phys =3D <&serdes0_pcie_link>;
phy-names =3D "pcie-phy";
- ti,syscon-pcie-ctrl =3D <&scm_conf 0x4074>;
+ ti,syscon-pcie-ctrl =3D <&pcie1_ctrl 0x0>;
};
};
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dt=
s/ti/k3-j7200-main.dtsi
index 5ab510a0605f..dbb000657377 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -32,6 +32,11 @@ scm_conf: scm-conf@100000 {
#size-cells =3D <1>;
ranges =3D <0x00 0x00 0x00100000 0x1c000>;
=20
+ pcie1_ctrl: pcie-ctrl@4074 {
+ compatible =3D "ti,j784s4-pcie-ctrl", "syscon";
+ reg =3D <0x4074 0x4>;
+ };
+
serdes_ln_ctrl: mux-controller@4080 {
compatible =3D "reg-mux";
reg =3D <0x4080 0x20>;
@@ -764,7 +769,7 @@ pcie1_rc: pcie@2910000 {
interrupt-names =3D "link_state";
interrupts =3D <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
device_type =3D "pci";
- ti,syscon-pcie-ctrl =3D <&scm_conf 0x4074>;
+ ti,syscon-pcie-ctrl =3D <&pcie1_ctrl 0x0>;
max-link-speed =3D <3>;
num-lanes =3D <4>;
power-domains =3D <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
--=20
2.34.1
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From: Jayesh Choudhary <j-choudhary@ti.com>
To: <robh@kernel.org>, <krzk+dt@kernel.org>, <conor+dt@kernel.org>,
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Subject: [PATCH v2 4/5] arm64: dts: ti: k3-j721s2: Add PCIe ctrl node to
scm_conf region
Date: Wed, 2 Apr 2025 17:02:00 +0530
Message-ID: <20250402113201.151195-5-j-choudhary@ti.com>
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From: Andrew Davis <afd@ti.com>
This region is used for controlling the function of the PCIe IP. It is
compatible with "ti,j784s4-pcie-ctrl", add this here and use it with
the PCIe node.
Signed-off-by: Andrew Davis <afd@ti.com>
[j-choudhary@ti.com: Add changes to k3-am68-sk-base-board-pcie1-ep.dtso]
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
arch/arm64/boot/dts/ti/k3-am68-sk-base-board-pcie1-ep.dtso | 2 +-
arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso | 2 +-
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 7 ++++++-
3 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board-pcie1-ep.dtso b/a=
rch/arm64/boot/dts/ti/k3-am68-sk-base-board-pcie1-ep.dtso
index 455736e378cc..ba521d661144 100644
--- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board-pcie1-ep.dtso
+++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board-pcie1-ep.dtso
@@ -48,6 +48,6 @@ pcie1_ep: pcie-ep@2910000 {
dma-coherent;
phys =3D <&serdes0_pcie_link>;
phy-names =3D "pcie-phy";
- ti,syscon-pcie-ctrl =3D <&scm_conf 0x074>;
+ ti,syscon-pcie-ctrl =3D <&pcie1_ctrl 0x0>;
};
};
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso b/arch/arm6=
4/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso
index 5ff390915b75..8c2cd99cf2b4 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso
@@ -38,7 +38,7 @@ pcie1_ep: pcie-ep@2910000 {
reg-names =3D "intd_cfg", "user_cfg", "reg", "mem";
interrupt-names =3D "link_state";
interrupts =3D <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
- ti,syscon-pcie-ctrl =3D <&scm_conf 0x074>;
+ ti,syscon-pcie-ctrl =3D <&pcie1_ctrl 0x0>;
max-link-speed =3D <3>;
num-lanes =3D <1>;
power-domains =3D <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/d=
ts/ti/k3-j721s2-main.dtsi
index 92bf48fdbeba..c0c2b95d4652 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -57,6 +57,11 @@ phy_gmii_sel_cpsw: phy@34 {
#phy-cells =3D <1>;
};
=20
+ pcie1_ctrl: pcie-ctrl@74 {
+ compatible =3D "ti,j784s4-pcie-ctrl", "syscon";
+ reg =3D <0x74 0x4>;
+ };
+
serdes_ln_ctrl: mux-controller@80 {
compatible =3D "reg-mux";
reg =3D <0x80 0x10>;
@@ -1399,7 +1404,7 @@ pcie1_rc: pcie@2910000 {
interrupt-names =3D "link_state";
interrupts =3D <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
device_type =3D "pci";
- ti,syscon-pcie-ctrl =3D <&scm_conf 0x074>;
+ ti,syscon-pcie-ctrl =3D <&pcie1_ctrl 0x0>;
max-link-speed =3D <3>;
num-lanes =3D <4>;
power-domains =3D <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
--=20
2.34.1
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To: <robh@kernel.org>, <krzk+dt@kernel.org>, <conor+dt@kernel.org>,
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<j-choudhary@ti.com>
Subject: [PATCH v2 5/5] arm64: dts: ti: k3-am64: Add PCIe ctrl node to
main_conf region
Date: Wed, 2 Apr 2025 17:02:01 +0530
Message-ID: <20250402113201.151195-6-j-choudhary@ti.com>
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From: Andrew Davis <afd@ti.com>
This region is used for controlling the function of the PCIe IP. It is
compatible with "ti,j784s4-pcie-ctrl", add this here and use it with
the PCIe node.
Signed-off-by: Andrew Davis <afd@ti.com>
[j-choudhary@ti.com: Add changes to k3-am642-evm-pcie0-ep.dtso]
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 7 ++++++-
arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso | 2 +-
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts=
/ti/k3-am64-main.dtsi
index 324eb44c258d..d872a624601c 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -51,6 +51,11 @@ chipid@14 {
reg =3D <0x00000014 0x4>;
};
=20
+ pcie0_ctrl: pcie-ctrl@4070 {
+ compatible =3D "ti,j784s4-pcie-ctrl", "syscon";
+ reg =3D <0x4070 0x4>;
+ };
+
serdes_ln_ctrl: mux-controller@4080 {
compatible =3D "reg-mux";
reg =3D <0x4080 0x4>;
@@ -1036,7 +1041,7 @@ pcie0_rc: pcie@f102000 {
interrupt-names =3D "link_state";
interrupts =3D <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
device_type =3D "pci";
- ti,syscon-pcie-ctrl =3D <&main_conf 0x4070>;
+ ti,syscon-pcie-ctrl =3D <&pcie0_ctrl 0x0>;
max-link-speed =3D <2>;
num-lanes =3D <1>;
power-domains =3D <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso b/arch/arm64=
/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso
index 6b029539e0db..432751774853 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso
+++ b/arch/arm64/boot/dts/ti/k3-am642-evm-pcie0-ep.dtso
@@ -46,6 +46,6 @@ pcie0_ep: pcie-ep@f102000 {
max-functions =3D /bits/ 8 <1>;
phys =3D <&serdes0_pcie_link>;
phy-names =3D "pcie-phy";
- ti,syscon-pcie-ctrl =3D <&main_conf 0x4070>;
+ ti,syscon-pcie-ctrl =3D <&pcie0_ctrl 0x0>;
};
};
--=20
2.34.1