Add the System Timer Module description found on the NXP s32 platform
and the compatible for the s32g2 variant.
Cc: Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>
Cc: Thomas Fossati <thomas.fossati@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
.../bindings/timer/nxp,s32g2-stm.yaml | 53 +++++++++++++++++++
1 file changed, 53 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/nxp,s32g2-stm.yaml
diff --git a/Documentation/devicetree/bindings/timer/nxp,s32g2-stm.yaml b/Documentation/devicetree/bindings/timer/nxp,s32g2-stm.yaml
new file mode 100644
index 000000000000..2016f346b2ee
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/nxp,s32g2-stm.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/nxp,s32g2-stm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP System Timer Module (STM)
+
+maintainers:
+ - Daniel Lezcano <daniel.lezcano@kernel.org>
+
+description:
+ The System Timer Module supports commonly required system and application
+ software timing functions. STM includes a 32-bit count-up timer and four
+ 32-bit compare channels with a separate interrupt source for each channel.
+ The timer is driven by the STM module clock divided by an 8-bit prescale
+ value.
+
+properties:
+ compatible:
+ oneOf:
+ - const: nxp,s32g2-stm
+ - items:
+ - const: nxp,s32g3-stm
+ - const: nxp,s32g2-stm
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ timer@4011c000 {
+ compatible = "nxp,s32g2-stm";
+ reg = <0x4011c000 0x3000>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 0x3b>;
+ };
--
2.43.0On 4/2/2025 12:07 PM, Daniel Lezcano wrote:
[ ... ]
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + timer@4011c000 {
> + compatible = "nxp,s32g2-stm";
> + reg = <0x4011c000 0x3000>;
> + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 0x3b>;
> + };
The S32G reference manual specifies two clocks for the STM module: one
for the registers and another for the counter itself. Shouldn't both
clocks be represented in the bindings?
--
Regards,
Ghennadi
On 03/04/2025 08:33, Ghennadi Procopciuc wrote:
> On 4/2/2025 12:07 PM, Daniel Lezcano wrote:
> [ ... ]
>> +examples:
>> + - |
>> + #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> + timer@4011c000 {
>> + compatible = "nxp,s32g2-stm";
>> + reg = <0x4011c000 0x3000>;
>> + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&clks 0x3b>;
>> + };
>
> The S32G reference manual specifies two clocks for the STM module: one
> for the registers and another for the counter itself. Shouldn't both
> clocks be represented in the bindings?
AFAICS, there are two clocks as described in the documentation for the
s32g2 page 843, section 23.7.3 Timer modules.
The module and the register clock are fed by the XBAR_DIV3_CLK which is
an system clock always-on.
page 1994, 40.5.4 Clocking, the documentation says: "This module has no
clocking considerations."
From my understanding, we should not describe the XBAR_DIV3_CLK as it
is a system clock.
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On 03/04/2025 17:21, Daniel Lezcano wrote:
> On 03/04/2025 08:33, Ghennadi Procopciuc wrote:
>> On 4/2/2025 12:07 PM, Daniel Lezcano wrote:
>> [ ... ]
>>> +examples:
>>> + - |
>>> + #include <dt-bindings/interrupt-controller/arm-gic.h>
>>> +
>>> + timer@4011c000 {
>>> + compatible = "nxp,s32g2-stm";
>>> + reg = <0x4011c000 0x3000>;
>>> + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
>>> + clocks = <&clks 0x3b>;
>>> + };
>>
>> The S32G reference manual specifies two clocks for the STM module: one
>> for the registers and another for the counter itself. Shouldn't both
>> clocks be represented in the bindings?
>
> AFAICS, there are two clocks as described in the documentation for the
> s32g2 page 843, section 23.7.3 Timer modules.
>
> The module and the register clock are fed by the XBAR_DIV3_CLK which is
> an system clock always-on.
>
> page 1994, 40.5.4 Clocking, the documentation says: "This module has no
> clocking considerations."
>
> From my understanding, we should not describe the XBAR_DIV3_CLK as it
> is a system clock.
Can you clarify for the STM if you still want to change the binding ?
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On 4/7/2025 10:37 AM, Daniel Lezcano wrote:
> On 03/04/2025 17:21, Daniel Lezcano wrote:
>> On 03/04/2025 08:33, Ghennadi Procopciuc wrote:
>>> On 4/2/2025 12:07 PM, Daniel Lezcano wrote:
>>> [ ... ]
>>>> +examples:
>>>> + - |
>>>> + #include <dt-bindings/interrupt-controller/arm-gic.h>
>>>> +
>>>> + timer@4011c000 {
>>>> + compatible = "nxp,s32g2-stm";
>>>> + reg = <0x4011c000 0x3000>;
>>>> + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
>>>> + clocks = <&clks 0x3b>;
>>>> + };
>>>
>>> The S32G reference manual specifies two clocks for the STM module: one
>>> for the registers and another for the counter itself. Shouldn't both
>>> clocks be represented in the bindings?
>>
>> AFAICS, there are two clocks as described in the documentation for the
>> s32g2 page 843, section 23.7.3 Timer modules.
>>
>> The module and the register clock are fed by the XBAR_DIV3_CLK which
>> is an system clock always-on.
>>
>> page 1994, 40.5.4 Clocking, the documentation says: "This module has
>> no clocking considerations."
>>
>> From my understanding, we should not describe the XBAR_DIV3_CLK as it
>> is a system clock.
>
> Can you clarify for the STM if you still want to change the binding ?
>
Yes, I still believe the suggestion is relevant.
--
Regards,
Ghennadi
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