Update kcpuid's CSV file to version 2.3, as generated by x86-cpuid-db.
Summary of the v2.3 changes:
* Per H. Peter Anvin's feedback, leaf 0x3 is not unique to Transmeta as
the CSV file earlier claimed. Since leaf 0x3's format differs between
Intel and Transmeta, and the project does not yet support having the
same CPUID bitfield with varying interpretations across vendors, leaf
0x3 is removed for now. Given that Intel discontinued support for PSN
from Pentium 4 onward, and Linux force disables it on early boot for
privacy concerns, this should have minimal impact.
* Leaf 0x80000021: Make bitfield IDs and descriptions coherent with each
other. Remove "_support" from bitfield IDs, as no other leaf has such
convention.
Reported-by: "H. Peter Anvin" <hpa@zytor.com>
Closes: https://lkml.kernel.org/r/C7684E03-36E0-4D58-B6F0-78F4DB82D737@zytor.com
Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
Link: https://gitlab.com/x86-cpuid.org/x86-cpuid-db/-/blob/v2.3/CHANGELOG.rst
---
tools/arch/x86/kcpuid/cpuid.csv | 30 +++++++++++-------------------
1 file changed, 11 insertions(+), 19 deletions(-)
diff --git a/tools/arch/x86/kcpuid/cpuid.csv b/tools/arch/x86/kcpuid/cpuid.csv
index 9613e09cbfb3..8d25b0b49f3b 100644
--- a/tools/arch/x86/kcpuid/cpuid.csv
+++ b/tools/arch/x86/kcpuid/cpuid.csv
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: CC0-1.0
-# Generator: x86-cpuid-db v2.2
+# Generator: x86-cpuid-db v2.3
#
# Auto-generated file.
@@ -116,14 +116,6 @@
0x2, 0, edx, 30:24, desc15 , Descriptor #15
0x2, 0, edx, 31, edx_invalid , Descriptors 12-15 are invalid if set
-# Leaf 3H
-# Transmeta Processor Serial Number (PSN)
-
- 0x3, 0, eax, 31:0, cpu_psn_0 , Processor Serial Number bytes 0 - 3
- 0x3, 0, ebx, 31:0, cpu_psn_1 , Processor Serial Number bytes 4 - 7
- 0x3, 0, ecx, 31:0, cpu_psn_2 , Processor Serial Number bytes 8 - 11
- 0x3, 0, edx, 31:0, cpu_psn_3 , Processor Serial Number bytes 12 - 15
-
# Leaf 4H
# Intel deterministic cache parameters
@@ -1020,20 +1012,20 @@
0x80000021, 0, eax, 0, no_nested_data_bp , No nested data breakpoints
0x80000021, 0, eax, 1, fsgs_non_serializing , WRMSR to {FS,GS,KERNEL_GS}_BASE is non-serializing
0x80000021, 0, eax, 2, lfence_rdtsc , LFENCE always serializing / synchronizes RDTSC
-0x80000021, 0, eax, 3, smm_page_cfg_lock , SMM paging configuration lock is supported
+0x80000021, 0, eax, 3, smm_page_cfg_lock , SMM paging configuration lock
0x80000021, 0, eax, 6, null_sel_clr_base , Null selector clears base
-0x80000021, 0, eax, 7, upper_addr_ignore , EFER MSR Upper Address Ignore Enable bit supported
-0x80000021, 0, eax, 8, autoibrs , EFER MSR Automatic IBRS enable bit supported
-0x80000021, 0, eax, 9, no_smm_ctl_msr , SMM_CTL MSR (0xc0010116) is not present
-0x80000021, 0, eax, 10, fsrs_supported , Fast Short Rep STOSB (FSRS) is supported
-0x80000021, 0, eax, 11, fsrc_supported , Fast Short Rep CMPSB (FSRC) is supported
-0x80000021, 0, eax, 13, prefetch_ctl_msr , Prefetch control MSR is supported
+0x80000021, 0, eax, 7, upper_addr_ignore , EFER MSR Upper Address Ignore
+0x80000021, 0, eax, 8, autoibrs , EFER MSR Automatic IBRS
+0x80000021, 0, eax, 9, no_smm_ctl_msr , SMM_CTL MSR (0xc0010116) is not available
+0x80000021, 0, eax, 10, fsrs , Fast Short Rep STOSB
+0x80000021, 0, eax, 11, fsrc , Fast Short Rep CMPSB
+0x80000021, 0, eax, 13, prefetch_ctl_msr , Prefetch control MSR is available
0x80000021, 0, eax, 16, opcode_reclaim , Reserves opcode space
0x80000021, 0, eax, 17, user_cpuid_disable , #GP when executing CPUID at CPL > 0 is supported
-0x80000021, 0, eax, 18, epsf_supported , Enhanced Predictive Store Forwarding (EPSF) is supported
+0x80000021, 0, eax, 18, epsf , Enhanced Predictive Store Forwarding
0x80000021, 0, eax, 22, wl_feedback , Workload-based heuristic feedback to OS
-0x80000021, 0, eax, 24, eraps_support , Enhanced Return Address Predictor Security
-0x80000021, 0, eax, 27, sbpb , Support for the Selective Branch Predictor Barrier
+0x80000021, 0, eax, 24, eraps , Enhanced Return Address Predictor Security
+0x80000021, 0, eax, 27, sbpb , Selective Branch Predictor Barrier
0x80000021, 0, eax, 28, ibpb_brtype , Branch predictions flushed from CPU branch predictor
0x80000021, 0, eax, 29, srso_no , CPU is not subject to the SRSO vulnerability
0x80000021, 0, eax, 30, srso_uk_no , CPU is not vulnerable to SRSO at user-kernel boundary
--
2.48.1On March 12, 2025 7:37:36 AM PDT, "Ahmed S. Darwish" <darwi@linutronix.de> wrote:
>Update kcpuid's CSV file to version 2.3, as generated by x86-cpuid-db.
>
>Summary of the v2.3 changes:
>
>* Per H. Peter Anvin's feedback, leaf 0x3 is not unique to Transmeta as
> the CSV file earlier claimed. Since leaf 0x3's format differs between
> Intel and Transmeta, and the project does not yet support having the
> same CPUID bitfield with varying interpretations across vendors, leaf
> 0x3 is removed for now. Given that Intel discontinued support for PSN
> from Pentium 4 onward, and Linux force disables it on early boot for
> privacy concerns, this should have minimal impact.
>
>* Leaf 0x80000021: Make bitfield IDs and descriptions coherent with each
> other. Remove "_support" from bitfield IDs, as no other leaf has such
> convention.
>
>Reported-by: "H. Peter Anvin" <hpa@zytor.com>
>Closes: https://lkml.kernel.org/r/C7684E03-36E0-4D58-B6F0-78F4DB82D737@zytor.com
>Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
>Link: https://gitlab.com/x86-cpuid.org/x86-cpuid-db/-/blob/v2.3/CHANGELOG.rst
>---
> tools/arch/x86/kcpuid/cpuid.csv | 30 +++++++++++-------------------
> 1 file changed, 11 insertions(+), 19 deletions(-)
>
>diff --git a/tools/arch/x86/kcpuid/cpuid.csv b/tools/arch/x86/kcpuid/cpuid.csv
>index 9613e09cbfb3..8d25b0b49f3b 100644
>--- a/tools/arch/x86/kcpuid/cpuid.csv
>+++ b/tools/arch/x86/kcpuid/cpuid.csv
>@@ -1,5 +1,5 @@
> # SPDX-License-Identifier: CC0-1.0
>-# Generator: x86-cpuid-db v2.2
>+# Generator: x86-cpuid-db v2.3
>
> #
> # Auto-generated file.
>@@ -116,14 +116,6 @@
> 0x2, 0, edx, 30:24, desc15 , Descriptor #15
> 0x2, 0, edx, 31, edx_invalid , Descriptors 12-15 are invalid if set
>
>-# Leaf 3H
>-# Transmeta Processor Serial Number (PSN)
>-
>- 0x3, 0, eax, 31:0, cpu_psn_0 , Processor Serial Number bytes 0 - 3
>- 0x3, 0, ebx, 31:0, cpu_psn_1 , Processor Serial Number bytes 4 - 7
>- 0x3, 0, ecx, 31:0, cpu_psn_2 , Processor Serial Number bytes 8 - 11
>- 0x3, 0, edx, 31:0, cpu_psn_3 , Processor Serial Number bytes 12 - 15
>-
> # Leaf 4H
> # Intel deterministic cache parameters
>
>@@ -1020,20 +1012,20 @@
> 0x80000021, 0, eax, 0, no_nested_data_bp , No nested data breakpoints
> 0x80000021, 0, eax, 1, fsgs_non_serializing , WRMSR to {FS,GS,KERNEL_GS}_BASE is non-serializing
> 0x80000021, 0, eax, 2, lfence_rdtsc , LFENCE always serializing / synchronizes RDTSC
>-0x80000021, 0, eax, 3, smm_page_cfg_lock , SMM paging configuration lock is supported
>+0x80000021, 0, eax, 3, smm_page_cfg_lock , SMM paging configuration lock
> 0x80000021, 0, eax, 6, null_sel_clr_base , Null selector clears base
>-0x80000021, 0, eax, 7, upper_addr_ignore , EFER MSR Upper Address Ignore Enable bit supported
>-0x80000021, 0, eax, 8, autoibrs , EFER MSR Automatic IBRS enable bit supported
>-0x80000021, 0, eax, 9, no_smm_ctl_msr , SMM_CTL MSR (0xc0010116) is not present
>-0x80000021, 0, eax, 10, fsrs_supported , Fast Short Rep STOSB (FSRS) is supported
>-0x80000021, 0, eax, 11, fsrc_supported , Fast Short Rep CMPSB (FSRC) is supported
>-0x80000021, 0, eax, 13, prefetch_ctl_msr , Prefetch control MSR is supported
>+0x80000021, 0, eax, 7, upper_addr_ignore , EFER MSR Upper Address Ignore
>+0x80000021, 0, eax, 8, autoibrs , EFER MSR Automatic IBRS
>+0x80000021, 0, eax, 9, no_smm_ctl_msr , SMM_CTL MSR (0xc0010116) is not available
>+0x80000021, 0, eax, 10, fsrs , Fast Short Rep STOSB
>+0x80000021, 0, eax, 11, fsrc , Fast Short Rep CMPSB
>+0x80000021, 0, eax, 13, prefetch_ctl_msr , Prefetch control MSR is available
> 0x80000021, 0, eax, 16, opcode_reclaim , Reserves opcode space
> 0x80000021, 0, eax, 17, user_cpuid_disable , #GP when executing CPUID at CPL > 0 is supported
>-0x80000021, 0, eax, 18, epsf_supported , Enhanced Predictive Store Forwarding (EPSF) is supported
>+0x80000021, 0, eax, 18, epsf , Enhanced Predictive Store Forwarding
> 0x80000021, 0, eax, 22, wl_feedback , Workload-based heuristic feedback to OS
>-0x80000021, 0, eax, 24, eraps_support , Enhanced Return Address Predictor Security
>-0x80000021, 0, eax, 27, sbpb , Support for the Selective Branch Predictor Barrier
>+0x80000021, 0, eax, 24, eraps , Enhanced Return Address Predictor Security
>+0x80000021, 0, eax, 27, sbpb , Selective Branch Predictor Barrier
> 0x80000021, 0, eax, 28, ibpb_brtype , Branch predictions flushed from CPU branch predictor
> 0x80000021, 0, eax, 29, srso_no , CPU is not subject to the SRSO vulnerability
> 0x80000021, 0, eax, 30, srso_uk_no , CPU is not vulnerable to SRSO at user-kernel boundary
As I said, you can simply treat leaf 3 as raw 128-bit hexadecimal number; there really isn't a need to "interpret" it since the only meaningful use of it is as a unique identifier combined with vendor-FMS.
Hi,
On Wed, 12 Mar 2025, H. Peter Anvin wrote:
>
> On Wed, 12 Mar 2025, "Ahmed S. Darwish" wrote:
> >
> > Update kcpuid's CSV file to version 2.3, as generated by x86-cpuid-db.
> >
> > Summary of the v2.3 changes:
> >
> > * Per H. Peter Anvin's feedback, leaf 0x3 is not unique to Transmeta as
> > the CSV file earlier claimed. Since leaf 0x3's format differs between
> > Intel and Transmeta, and the project does not yet support having the
> > same CPUID bitfield with varying interpretations across vendors, leaf
> > 0x3 is removed for now. Given that Intel discontinued support for PSN
> > from Pentium 4 onward, and Linux force disables it on early boot for
> > privacy concerns, this should have minimal impact.
> >
> > * Leaf 0x80000021: Make bitfield IDs and descriptions coherent with each
> > other. Remove "_support" from bitfield IDs, as no other leaf has such
> > convention.
> >
> > Reported-by: "H. Peter Anvin" <hpa@zytor.com>
> > Closes: https://lkml.kernel.org/r/C7684E03-36E0-4D58-B6F0-78F4DB82D737@zytor.com
> > Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
> > Link: https://gitlab.com/x86-cpuid.org/x86-cpuid-db/-/blob/v2.3/CHANGELOG.rst
> > ---
>
> As I said, you can simply treat leaf 3 as raw 128-bit hexadecimal
> number; there really isn't a need to "interpret" it since the only
> meaningful use of it is as a unique identifier combined with
> vendor-FMS.
Yes, but this would introduce special-case leaf handing in kcpuid.
So far, the kcpuid code is "dumb". It just parses the CPUID bitfields
according to what's in the CSV file, with no intrinsic knowledge of any
certain leaf by the C code.
This is why, for example, kcpuid does not print CPU vendor strings in
human readable form. It just dumps whatever is there in the various
leaves bitfields:
$ kcpuid --all -l 0
max_std_leaf : 0x16
cpu_vendorid_0 : 0x756e6547
cpu_vendorid_2 : 0x6c65746e
cpu_vendorid_1 : 0x49656e69
$ kcpuid --all --detail -l 0
CPUID_0x0_EAX[0x0]:
max_std_leaf : 0x16 - Highest standard CPUID leaf supported
CPUID_0x0_EBX[0x0]:
cpu_vendorid_0 : 0x756e6547 - CPU vendor ID string bytes 0 - 3
CPUID_0x0_ECX[0x0]:
cpu_vendorid_2 : 0x6c65746e - CPU vendor ID string bytes 8 - 11
CPUID_0x0_EDX[0x0]:
cpu_vendorid_1 : 0x49656e69 - CPU vendor ID string bytes 4 - 7
We can extend kcpuid to handle a special case for the PSN, but if we
gonna do that, then it would be much better to start that with CPUID
leaves that actually matter: CPU vendor strings, leaf 0x2 1-byte
descriptor semantics, etc., etc.
Given all that, can we please move on regarding this leaf 0x3PSN thing?
IMHO, there's no reason to block the series because of that :(
Thanks!
--
Ahmed S. Darwish
Linutronix GmbH
© 2016 - 2025 Red Hat, Inc.