From: James Clark <james.clark@arm.com>
Convert TRFCR to automatic generation. Add separate definitions for ELx
and EL2 as TRFCR_EL1 doesn't have CX. This also mirrors the previous
definition so no code change is required.
Also add TRFCR_EL12 which will start to be used in a later commit.
Unfortunately, to avoid breaking the Perf build with duplicate
definition errors, the tools copy of the sysreg.h header needs to be
updated at the same time rather than the usual second commit. This is
because the generated version of sysreg
(arch/arm64/include/generated/asm/sysreg-defs.h), is currently shared
and tools/ does not have its own copy.
Reviewed-by: Mark Brown <broonie@kernel.org>
Signed-off-by: James Clark <james.clark@arm.com>
Signed-off-by: James Clark <james.clark@linaro.org>
---
arch/arm64/include/asm/sysreg.h | 12 ---------
arch/arm64/tools/sysreg | 36 +++++++++++++++++++++++++++
tools/arch/arm64/include/asm/sysreg.h | 12 ---------
3 files changed, 36 insertions(+), 24 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index b8303a83c0bf..808f65818b91 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -283,8 +283,6 @@
#define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
#define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
-#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1)
-
#define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2)
#define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0)
@@ -519,7 +517,6 @@
#define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0)
#define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2)
-#define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1)
#define SYS_VNCR_EL2 sys_reg(3, 4, 2, 2, 0)
#define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6)
#define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
@@ -983,15 +980,6 @@
/* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
#define SYS_MPIDR_SAFE_VAL (BIT(31))
-#define TRFCR_ELx_TS_SHIFT 5
-#define TRFCR_ELx_TS_MASK ((0x3UL) << TRFCR_ELx_TS_SHIFT)
-#define TRFCR_ELx_TS_VIRTUAL ((0x1UL) << TRFCR_ELx_TS_SHIFT)
-#define TRFCR_ELx_TS_GUEST_PHYSICAL ((0x2UL) << TRFCR_ELx_TS_SHIFT)
-#define TRFCR_ELx_TS_PHYSICAL ((0x3UL) << TRFCR_ELx_TS_SHIFT)
-#define TRFCR_EL2_CX BIT(3)
-#define TRFCR_ELx_ExTRE BIT(1)
-#define TRFCR_ELx_E0TRE BIT(0)
-
/* GIC Hypervisor interface registers */
/* ICH_MISR_EL2 bit definitions */
#define ICH_MISR_EOI (1 << 0)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 4ba167089e2a..ef8a06e180b3 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -1997,6 +1997,22 @@ Sysreg CPACR_EL1 3 0 1 0 2
Fields CPACR_ELx
EndSysreg
+SysregFields TRFCR_ELx
+Res0 63:7
+UnsignedEnum 6:5 TS
+ 0b0001 VIRTUAL
+ 0b0010 GUEST_PHYSICAL
+ 0b0011 PHYSICAL
+EndEnum
+Res0 4:2
+Field 1 ExTRE
+Field 0 E0TRE
+EndSysregFields
+
+Sysreg TRFCR_EL1 3 0 1 2 1
+Fields TRFCR_ELx
+EndSysreg
+
Sysreg SMPRI_EL1 3 0 1 2 4
Res0 63:4
Field 3:0 PRIORITY
@@ -2546,6 +2562,22 @@ Field 1 ICIALLU
Field 0 ICIALLUIS
EndSysreg
+Sysreg TRFCR_EL2 3 4 1 2 1
+Res0 63:7
+UnsignedEnum 6:5 TS
+ 0b0000 USE_TRFCR_EL1_TS
+ 0b0001 VIRTUAL
+ 0b0010 GUEST_PHYSICAL
+ 0b0011 PHYSICAL
+EndEnum
+Res0 4
+Field 3 CX
+Res0 2
+Field 1 E2TRE
+Field 0 E0HTRE
+EndSysreg
+
+
Sysreg HDFGRTR_EL2 3 4 3 1 4
Field 63 PMBIDR_EL1
Field 62 nPMSNEVFR_EL1
@@ -2956,6 +2988,10 @@ Sysreg ZCR_EL12 3 5 1 2 0
Fields ZCR_ELx
EndSysreg
+Sysreg TRFCR_EL12 3 5 1 2 1
+Fields TRFCR_ELx
+EndSysreg
+
Sysreg SMCR_EL12 3 5 1 2 6
Fields SMCR_ELx
EndSysreg
diff --git a/tools/arch/arm64/include/asm/sysreg.h b/tools/arch/arm64/include/asm/sysreg.h
index 345e81e0d2b3..150416682e2c 100644
--- a/tools/arch/arm64/include/asm/sysreg.h
+++ b/tools/arch/arm64/include/asm/sysreg.h
@@ -283,8 +283,6 @@
#define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
#define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
-#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1)
-
#define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2)
#define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0)
@@ -519,7 +517,6 @@
#define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0)
#define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2)
-#define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1)
#define SYS_VNCR_EL2 sys_reg(3, 4, 2, 2, 0)
#define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6)
#define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
@@ -983,15 +980,6 @@
/* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
#define SYS_MPIDR_SAFE_VAL (BIT(31))
-#define TRFCR_ELx_TS_SHIFT 5
-#define TRFCR_ELx_TS_MASK ((0x3UL) << TRFCR_ELx_TS_SHIFT)
-#define TRFCR_ELx_TS_VIRTUAL ((0x1UL) << TRFCR_ELx_TS_SHIFT)
-#define TRFCR_ELx_TS_GUEST_PHYSICAL ((0x2UL) << TRFCR_ELx_TS_SHIFT)
-#define TRFCR_ELx_TS_PHYSICAL ((0x3UL) << TRFCR_ELx_TS_SHIFT)
-#define TRFCR_EL2_CX BIT(3)
-#define TRFCR_ELx_ExTRE BIT(1)
-#define TRFCR_ELx_E0TRE BIT(0)
-
/* GIC Hypervisor interface registers */
/* ICH_MISR_EL2 bit definitions */
#define ICH_MISR_EOI (1 << 0)
--
2.34.1On Tue, 07 Jan 2025 11:32:43 +0000,
James Clark <james.clark@linaro.org> wrote:
>
> From: James Clark <james.clark@arm.com>
>
> Convert TRFCR to automatic generation. Add separate definitions for ELx
> and EL2 as TRFCR_EL1 doesn't have CX. This also mirrors the previous
> definition so no code change is required.
>
> Also add TRFCR_EL12 which will start to be used in a later commit.
>
> Unfortunately, to avoid breaking the Perf build with duplicate
> definition errors, the tools copy of the sysreg.h header needs to be
> updated at the same time rather than the usual second commit. This is
> because the generated version of sysreg
> (arch/arm64/include/generated/asm/sysreg-defs.h), is currently shared
> and tools/ does not have its own copy.
>
> Reviewed-by: Mark Brown <broonie@kernel.org>
> Signed-off-by: James Clark <james.clark@arm.com>
> Signed-off-by: James Clark <james.clark@linaro.org>
I've added the following patch to the series, dropping the TCFCR_ELx
construct and fixing the code that makes use of it.
M.
From fc77862e06ca1c15e44b0c915da193bd8ed855bc Mon Sep 17 00:00:00 2001
From: Marc Zyngier <maz@kernel.org>
Date: Sun, 12 Jan 2025 13:08:59 +0000
Subject: [PATCH] arm64/sysreg: Get rid of TRFCR_ELx SysregFields
There is no such thing as TRFCR_ELx in the architecture.
What we have is TRFCR_EL1, for which TRFCR_EL12 is an accessor.
Rename TRFCR_ELx_* to TRFCR_EL1_*, and fix the bit of code using
these names.
Similarly, TRFCR_EL12 is redefined as a mapping to TRFCR_EL1.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Cc: James Clark <james.clark@linaro.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Mark Brown <broonie@kernel.org>
Cc: Will Deacon <will@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
---
arch/arm64/tools/sysreg | 8 ++------
.../hwtracing/coresight/coresight-etm4x-core.c | 16 ++++++++--------
.../hwtracing/coresight/coresight-etm4x-sysfs.c | 10 +++++-----
drivers/hwtracing/coresight/coresight-trbe.c | 2 +-
4 files changed, 16 insertions(+), 20 deletions(-)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 4c2c9c6767c93..ac5202e1df862 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -1999,7 +1999,7 @@ Field 17:16 ZEN
Res0 15:0
EndSysreg
-SysregFields TRFCR_ELx
+Sysreg TRFCR_EL1 3 0 1 2 1
Res0 63:7
UnsignedEnum 6:5 TS
0b0001 VIRTUAL
@@ -2011,10 +2011,6 @@ Field 1 ExTRE
Field 0 E0TRE
EndSysregFields
-Sysreg TRFCR_EL1 3 0 1 2 1
-Fields TRFCR_ELx
-EndSysreg
-
Sysreg SMPRI_EL1 3 0 1 2 4
Res0 63:4
Field 3:0 PRIORITY
@@ -2991,7 +2987,7 @@ Mapping ZCR_EL1
EndSysreg
Sysreg TRFCR_EL12 3 5 1 2 1
-Fields TRFCR_ELx
+Mapping TRFCR_EL1
EndSysreg
Sysreg SMCR_EL12 3 5 1 2 6
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index fbc4aa3785279..2c1a60577728e 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -275,7 +275,7 @@ static void etm4x_prohibit_trace(struct etmv4_drvdata *drvdata)
if (!drvdata->trfcr)
return;
- trfcr = drvdata->trfcr & ~(TRFCR_ELx_ExTRE | TRFCR_ELx_E0TRE);
+ trfcr = drvdata->trfcr & ~(TRFCR_EL1_ExTRE | TRFCR_EL1_E0TRE);
write_trfcr(trfcr);
kvm_tracing_set_el1_configuration(trfcr);
@@ -286,9 +286,9 @@ static u64 etm4x_get_kern_user_filter(struct etmv4_drvdata *drvdata)
u64 trfcr = drvdata->trfcr;
if (drvdata->config.mode & ETM_MODE_EXCL_KERN)
- trfcr &= ~TRFCR_ELx_ExTRE;
+ trfcr &= ~TRFCR_EL1_ExTRE;
if (drvdata->config.mode & ETM_MODE_EXCL_USER)
- trfcr &= ~TRFCR_ELx_E0TRE;
+ trfcr &= ~TRFCR_EL1_E0TRE;
return trfcr;
}
@@ -312,7 +312,7 @@ static void etm4x_allow_trace(struct etmv4_drvdata *drvdata)
return;
if (drvdata->config.mode & ETM_MODE_EXCL_HOST)
- trfcr = drvdata->trfcr & ~(TRFCR_ELx_ExTRE | TRFCR_ELx_E0TRE);
+ trfcr = drvdata->trfcr & ~(TRFCR_EL1_ExTRE | TRFCR_EL1_E0TRE);
else
trfcr = etm4x_get_kern_user_filter(drvdata);
@@ -320,7 +320,7 @@ static void etm4x_allow_trace(struct etmv4_drvdata *drvdata)
/* Set filters for guests and pass to KVM */
if (drvdata->config.mode & ETM_MODE_EXCL_GUEST)
- guest_trfcr = drvdata->trfcr & ~(TRFCR_ELx_ExTRE | TRFCR_ELx_E0TRE);
+ guest_trfcr = drvdata->trfcr & ~(TRFCR_EL1_ExTRE | TRFCR_EL1_E0TRE);
else
guest_trfcr = etm4x_get_kern_user_filter(drvdata);
@@ -1176,9 +1176,9 @@ static void cpu_detect_trace_filtering(struct etmv4_drvdata *drvdata)
* tracing at the kernel EL and EL0, forcing to use the
* virtual time as the timestamp.
*/
- trfcr = (TRFCR_ELx_TS_VIRTUAL |
- TRFCR_ELx_ExTRE |
- TRFCR_ELx_E0TRE);
+ trfcr = (TRFCR_EL1_TS_VIRTUAL |
+ TRFCR_EL1_ExTRE |
+ TRFCR_EL1_E0TRE);
/* If we are running at EL2, allow tracing the CONTEXTIDR_EL2. */
if (is_kernel_in_hyp_mode())
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
index a9f19629f3f84..c767f8ae4cf1d 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
@@ -2319,11 +2319,11 @@ static ssize_t ts_source_show(struct device *dev,
goto out;
}
- switch (drvdata->trfcr & TRFCR_ELx_TS_MASK) {
- case TRFCR_ELx_TS_VIRTUAL:
- case TRFCR_ELx_TS_GUEST_PHYSICAL:
- case TRFCR_ELx_TS_PHYSICAL:
- val = FIELD_GET(TRFCR_ELx_TS_MASK, drvdata->trfcr);
+ switch (drvdata->trfcr & TRFCR_EL1_TS_MASK) {
+ case TRFCR_EL1_TS_VIRTUAL:
+ case TRFCR_EL1_TS_GUEST_PHYSICAL:
+ case TRFCR_EL1_TS_PHYSICAL:
+ val = FIELD_GET(TRFCR_EL1_TS_MASK, drvdata->trfcr);
break;
default:
val = -1;
diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c
index d6eb0d525a4d6..fff67aac84181 100644
--- a/drivers/hwtracing/coresight/coresight-trbe.c
+++ b/drivers/hwtracing/coresight/coresight-trbe.c
@@ -1118,7 +1118,7 @@ static u64 cpu_prohibit_trace(void)
u64 trfcr = read_trfcr();
/* Prohibit tracing at EL0 & the kernel EL */
- write_trfcr(trfcr & ~(TRFCR_ELx_ExTRE | TRFCR_ELx_E0TRE));
+ write_trfcr(trfcr & ~(TRFCR_EL1_ExTRE | TRFCR_EL1_E0TRE));
/* Return the original value of the TRFCR */
return trfcr;
}
--
2.39.2
--
Without deviation from the norm, progress is not possible.
On 12/01/2025 1:58 pm, Marc Zyngier wrote:
> On Tue, 07 Jan 2025 11:32:43 +0000,
> James Clark <james.clark@linaro.org> wrote:
>>
>> From: James Clark <james.clark@arm.com>
>>
>> Convert TRFCR to automatic generation. Add separate definitions for ELx
>> and EL2 as TRFCR_EL1 doesn't have CX. This also mirrors the previous
>> definition so no code change is required.
>>
>> Also add TRFCR_EL12 which will start to be used in a later commit.
>>
>> Unfortunately, to avoid breaking the Perf build with duplicate
>> definition errors, the tools copy of the sysreg.h header needs to be
>> updated at the same time rather than the usual second commit. This is
>> because the generated version of sysreg
>> (arch/arm64/include/generated/asm/sysreg-defs.h), is currently shared
>> and tools/ does not have its own copy.
>>
>> Reviewed-by: Mark Brown <broonie@kernel.org>
>> Signed-off-by: James Clark <james.clark@arm.com>
>> Signed-off-by: James Clark <james.clark@linaro.org>
>
> I've added the following patch to the series, dropping the TCFCR_ELx
> construct and fixing the code that makes use of it.
>
> M.
>
> From fc77862e06ca1c15e44b0c915da193bd8ed855bc Mon Sep 17 00:00:00 2001
> From: Marc Zyngier <maz@kernel.org>
> Date: Sun, 12 Jan 2025 13:08:59 +0000
> Subject: [PATCH] arm64/sysreg: Get rid of TRFCR_ELx SysregFields
>
> There is no such thing as TRFCR_ELx in the architecture.
> What we have is TRFCR_EL1, for which TRFCR_EL12 is an accessor.
>
> Rename TRFCR_ELx_* to TRFCR_EL1_*, and fix the bit of code using
> these names.
>
> Similarly, TRFCR_EL12 is redefined as a mapping to TRFCR_EL1.
>
I saw your 'mapping' patch but didn't pull it in for whatever reason. LGTM.
Reviewed-by: James Clark <james.clark@linaro.org>
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> Cc: James Clark <james.clark@linaro.org>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Cc: Mark Brown <broonie@kernel.org>
> Cc: Will Deacon <will@kernel.org>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> ---
> arch/arm64/tools/sysreg | 8 ++------
> .../hwtracing/coresight/coresight-etm4x-core.c | 16 ++++++++--------
> .../hwtracing/coresight/coresight-etm4x-sysfs.c | 10 +++++-----
> drivers/hwtracing/coresight/coresight-trbe.c | 2 +-
> 4 files changed, 16 insertions(+), 20 deletions(-)
>
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index 4c2c9c6767c93..ac5202e1df862 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -1999,7 +1999,7 @@ Field 17:16 ZEN
> Res0 15:0
> EndSysreg
>
> -SysregFields TRFCR_ELx
> +Sysreg TRFCR_EL1 3 0 1 2 1
> Res0 63:7
> UnsignedEnum 6:5 TS
> 0b0001 VIRTUAL
> @@ -2011,10 +2011,6 @@ Field 1 ExTRE
> Field 0 E0TRE
> EndSysregFields
>
> -Sysreg TRFCR_EL1 3 0 1 2 1
> -Fields TRFCR_ELx
> -EndSysreg
> -
> Sysreg SMPRI_EL1 3 0 1 2 4
> Res0 63:4
> Field 3:0 PRIORITY
> @@ -2991,7 +2987,7 @@ Mapping ZCR_EL1
> EndSysreg
>
> Sysreg TRFCR_EL12 3 5 1 2 1
> -Fields TRFCR_ELx
> +Mapping TRFCR_EL1
> EndSysreg
>
> Sysreg SMCR_EL12 3 5 1 2 6
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index fbc4aa3785279..2c1a60577728e 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -275,7 +275,7 @@ static void etm4x_prohibit_trace(struct etmv4_drvdata *drvdata)
> if (!drvdata->trfcr)
> return;
>
> - trfcr = drvdata->trfcr & ~(TRFCR_ELx_ExTRE | TRFCR_ELx_E0TRE);
> + trfcr = drvdata->trfcr & ~(TRFCR_EL1_ExTRE | TRFCR_EL1_E0TRE);
>
> write_trfcr(trfcr);
> kvm_tracing_set_el1_configuration(trfcr);
> @@ -286,9 +286,9 @@ static u64 etm4x_get_kern_user_filter(struct etmv4_drvdata *drvdata)
> u64 trfcr = drvdata->trfcr;
>
> if (drvdata->config.mode & ETM_MODE_EXCL_KERN)
> - trfcr &= ~TRFCR_ELx_ExTRE;
> + trfcr &= ~TRFCR_EL1_ExTRE;
> if (drvdata->config.mode & ETM_MODE_EXCL_USER)
> - trfcr &= ~TRFCR_ELx_E0TRE;
> + trfcr &= ~TRFCR_EL1_E0TRE;
>
> return trfcr;
> }
> @@ -312,7 +312,7 @@ static void etm4x_allow_trace(struct etmv4_drvdata *drvdata)
> return;
>
> if (drvdata->config.mode & ETM_MODE_EXCL_HOST)
> - trfcr = drvdata->trfcr & ~(TRFCR_ELx_ExTRE | TRFCR_ELx_E0TRE);
> + trfcr = drvdata->trfcr & ~(TRFCR_EL1_ExTRE | TRFCR_EL1_E0TRE);
> else
> trfcr = etm4x_get_kern_user_filter(drvdata);
>
> @@ -320,7 +320,7 @@ static void etm4x_allow_trace(struct etmv4_drvdata *drvdata)
>
> /* Set filters for guests and pass to KVM */
> if (drvdata->config.mode & ETM_MODE_EXCL_GUEST)
> - guest_trfcr = drvdata->trfcr & ~(TRFCR_ELx_ExTRE | TRFCR_ELx_E0TRE);
> + guest_trfcr = drvdata->trfcr & ~(TRFCR_EL1_ExTRE | TRFCR_EL1_E0TRE);
> else
> guest_trfcr = etm4x_get_kern_user_filter(drvdata);
>
> @@ -1176,9 +1176,9 @@ static void cpu_detect_trace_filtering(struct etmv4_drvdata *drvdata)
> * tracing at the kernel EL and EL0, forcing to use the
> * virtual time as the timestamp.
> */
> - trfcr = (TRFCR_ELx_TS_VIRTUAL |
> - TRFCR_ELx_ExTRE |
> - TRFCR_ELx_E0TRE);
> + trfcr = (TRFCR_EL1_TS_VIRTUAL |
> + TRFCR_EL1_ExTRE |
> + TRFCR_EL1_E0TRE);
>
> /* If we are running at EL2, allow tracing the CONTEXTIDR_EL2. */
> if (is_kernel_in_hyp_mode())
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> index a9f19629f3f84..c767f8ae4cf1d 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> @@ -2319,11 +2319,11 @@ static ssize_t ts_source_show(struct device *dev,
> goto out;
> }
>
> - switch (drvdata->trfcr & TRFCR_ELx_TS_MASK) {
> - case TRFCR_ELx_TS_VIRTUAL:
> - case TRFCR_ELx_TS_GUEST_PHYSICAL:
> - case TRFCR_ELx_TS_PHYSICAL:
> - val = FIELD_GET(TRFCR_ELx_TS_MASK, drvdata->trfcr);
> + switch (drvdata->trfcr & TRFCR_EL1_TS_MASK) {
> + case TRFCR_EL1_TS_VIRTUAL:
> + case TRFCR_EL1_TS_GUEST_PHYSICAL:
> + case TRFCR_EL1_TS_PHYSICAL:
> + val = FIELD_GET(TRFCR_EL1_TS_MASK, drvdata->trfcr);
> break;
> default:
> val = -1;
> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c
> index d6eb0d525a4d6..fff67aac84181 100644
> --- a/drivers/hwtracing/coresight/coresight-trbe.c
> +++ b/drivers/hwtracing/coresight/coresight-trbe.c
> @@ -1118,7 +1118,7 @@ static u64 cpu_prohibit_trace(void)
> u64 trfcr = read_trfcr();
>
> /* Prohibit tracing at EL0 & the kernel EL */
> - write_trfcr(trfcr & ~(TRFCR_ELx_ExTRE | TRFCR_ELx_E0TRE));
> + write_trfcr(trfcr & ~(TRFCR_EL1_ExTRE | TRFCR_EL1_E0TRE));
> /* Return the original value of the TRFCR */
> return trfcr;
> }
On Tue, 07 Jan 2025 11:32:43 +0000, James Clark <james.clark@linaro.org> wrote: > > From: James Clark <james.clark@arm.com> > > Convert TRFCR to automatic generation. Add separate definitions for ELx > and EL2 as TRFCR_EL1 doesn't have CX. This also mirrors the previous > definition so no code change is required. > > Also add TRFCR_EL12 which will start to be used in a later commit. > > Unfortunately, to avoid breaking the Perf build with duplicate > definition errors, the tools copy of the sysreg.h header needs to be > updated at the same time rather than the usual second commit. This is > because the generated version of sysreg > (arch/arm64/include/generated/asm/sysreg-defs.h), is currently shared > and tools/ does not have its own copy. > > Reviewed-by: Mark Brown <broonie@kernel.org> > Signed-off-by: James Clark <james.clark@arm.com> > Signed-off-by: James Clark <james.clark@linaro.org> > --- > arch/arm64/include/asm/sysreg.h | 12 --------- > arch/arm64/tools/sysreg | 36 +++++++++++++++++++++++++++ > tools/arch/arm64/include/asm/sysreg.h | 12 --------- > 3 files changed, 36 insertions(+), 24 deletions(-) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index b8303a83c0bf..808f65818b91 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -283,8 +283,6 @@ > #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5) > #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6) > > -#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1) > - > #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2) > > #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0) > @@ -519,7 +517,6 @@ > #define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0) > #define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2) > > -#define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1) > #define SYS_VNCR_EL2 sys_reg(3, 4, 2, 2, 0) > #define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6) > #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0) > @@ -983,15 +980,6 @@ > /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */ > #define SYS_MPIDR_SAFE_VAL (BIT(31)) > > -#define TRFCR_ELx_TS_SHIFT 5 > -#define TRFCR_ELx_TS_MASK ((0x3UL) << TRFCR_ELx_TS_SHIFT) > -#define TRFCR_ELx_TS_VIRTUAL ((0x1UL) << TRFCR_ELx_TS_SHIFT) > -#define TRFCR_ELx_TS_GUEST_PHYSICAL ((0x2UL) << TRFCR_ELx_TS_SHIFT) > -#define TRFCR_ELx_TS_PHYSICAL ((0x3UL) << TRFCR_ELx_TS_SHIFT) > -#define TRFCR_EL2_CX BIT(3) > -#define TRFCR_ELx_ExTRE BIT(1) > -#define TRFCR_ELx_E0TRE BIT(0) > - > /* GIC Hypervisor interface registers */ > /* ICH_MISR_EL2 bit definitions */ > #define ICH_MISR_EOI (1 << 0) > diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg > index 4ba167089e2a..ef8a06e180b3 100644 > --- a/arch/arm64/tools/sysreg > +++ b/arch/arm64/tools/sysreg > @@ -1997,6 +1997,22 @@ Sysreg CPACR_EL1 3 0 1 0 2 > Fields CPACR_ELx > EndSysreg > > +SysregFields TRFCR_ELx > +Res0 63:7 > +UnsignedEnum 6:5 TS > + 0b0001 VIRTUAL > + 0b0010 GUEST_PHYSICAL > + 0b0011 PHYSICAL > +EndEnum > +Res0 4:2 > +Field 1 ExTRE > +Field 0 E0TRE > +EndSysregFields > + > +Sysreg TRFCR_EL1 3 0 1 2 1 > +Fields TRFCR_ELx > +EndSysreg > + > Sysreg SMPRI_EL1 3 0 1 2 4 > Res0 63:4 > Field 3:0 PRIORITY > @@ -2546,6 +2562,22 @@ Field 1 ICIALLU > Field 0 ICIALLUIS > EndSysreg > > +Sysreg TRFCR_EL2 3 4 1 2 1 > +Res0 63:7 > +UnsignedEnum 6:5 TS > + 0b0000 USE_TRFCR_EL1_TS > + 0b0001 VIRTUAL > + 0b0010 GUEST_PHYSICAL > + 0b0011 PHYSICAL > +EndEnum > +Res0 4 > +Field 3 CX > +Res0 2 > +Field 1 E2TRE > +Field 0 E0HTRE > +EndSysreg > + > + > Sysreg HDFGRTR_EL2 3 4 3 1 4 > Field 63 PMBIDR_EL1 > Field 62 nPMSNEVFR_EL1 > @@ -2956,6 +2988,10 @@ Sysreg ZCR_EL12 3 5 1 2 0 > Fields ZCR_ELx > EndSysreg > > +Sysreg TRFCR_EL12 3 5 1 2 1 > +Fields TRFCR_ELx > +EndSysreg > + This (and the TRFCR_ELx nonsense) should be killed. I will fix it up locally. M. -- Without deviation from the norm, progress is not possible.
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